Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann

Contents
Background
Trends in Computing and Memory Technologies
1 Trends in Computing and Applications
2 Technology-Specific Limits
3 Computing Limitations
4 Memory Limitations
5 Book Scope and Organization
References
Devices and Models
Beyond-Silicon Computing: Nano-Technologies, Nano-Design, and Nano-Systems
1 Introduction
2 Emerging Nanotechnologies: Opportunities and Challenges
2.1 VLSI Circuit Benefits of One-Dimensional and Two-Dimensional Nanomaterials
2.2 Inherent Challenges in Emerging Nanotechnologies
3 Overcoming Challenges: Coordinated Nano-Fabrication + Nano-Design
3.1 VLSI CNFET Nano-Fabrication
3.2 VLSI CNFET Nano-Design
3.3 Rapid Co-optimization of Processing and Design to Overcome Nanotechnology Variations
3.4 Experimental CNFET Circuit Demonstrations
3.5 CNFET Technology Transfer to High Volume Commercial Manufacturing Facilities
4 Next-Generation Nano-Systems
4.1 Experimental 3D Nano-System Demonstrations
4.2 Three-Dimensional Nano-Systems in Commercial Foundries
5 Outlook
References
Innovative Memory Architectures Using Functionality Enhanced Devices
1 Introduction
2 Polarity Controllable SiNWFET Technology Overview
3 Silicon NanoWire FET Based True Single Phase Clock Flip-Flops
3.1 True Single-Phase Clock (TSPC) Flip-Flop
3.2 Standard PC SiNWFET Flip-Flop
3.3 Enhanced PC SiNWFET FF with Logic Operations
3.4 Discussion and Conclusions
4 Emerging Resistive Memories Architectures Using PC SiNWFETS
4.1 RRAM Technology
4.2 PC SiNWFET-OxRAM Co-Integration
4.3 Bitcell Design
4.4 Performances Metrics
4.5 Conclusions
5 Discussion and Perspectives
References
Interconnect and Integration Technology
1 Introduction
2 Photonic Links
2.1 Why Photonic Links?
2.2 Photonic Link Basics
2.3 Integration Technologies for Photonic Links
2.4 Challenges and Future Research/Design Perspectives
3 Monolithic 3D
3.1 Why Monolithic 3D Links?
3.2 M3D-Based Design
3.3 Challenges and Future Research/Design Perspectives
4 Wireless
4.1 Why Wireless Links?
4.2 Wireless Link Designs
4.3 Challenges and Future Research/Design Perspectives
5 Summary and Future Perspectives
References
Nanomagnetic Logic: From Devices to Systems
1 Introduction
1.1 A Brief History and Nomenclature
2 pNML Working Principle
2.1 Structure of the Magnetic Stack
2.2 Properties of the Hysteresis Loop
2.3 Defining Artificial Nucleation Centers
3 Computing with No Current
3.1 Coupling and Clocking Field
3.2 Basic Gates
3.3 Monolithic 3D Integration
3.4 Experimental Study of pNML Circuits
4 System-Level Design
4.1 Signal Synchronization
4.2 pNML as Co-Processor
4.3 EDA Tools and Compact Model
5 Design Example
6 Conclusion and Outlook
6.1 Material Improvements
6.2 ANC Engineering
6.3 Switching Field Distributions
6.4 Clocking Mechanism
6.5 System Level Explorations
6.6 Magnetic Devices for ULSI
References
Quantum Computing—An Emerging Computing Paradigm
1 Introduction
2 Gate Based Computing
2.1 Postulates of Quantum Mechanics
2.2 Unit of Quantum Information
2.3 Quantum Gates
2.4 Model Quantum Software
2.5 Qubit Realizations
3 Conclusion
References
Circuits and Architectures
A Modern Primer on Processing in Memory
1 Introduction
2 Major Trends Affecting Main Memory
3 The Need for Intelligent Memory Controllers to Enhance Memory Scaling
4 Perils of Processor-Centric Design
5 Processing-in-Memory (PIM): Technology Enablers and Two Approaches
5.1 New Technology Enablers: 3D-Stacked Memory and Non-Volatile Memory
5.2 Two Approaches: Processing Using Memory (PUM) Vs. Processing Near Memory (PNM)
6 Processing Using Memory (PUM)
6.1 RowClone
6.2 Ambit
6.3 Gather-Scatter DRAM
6.4 In-DRAM Security Primitives
7 Processing Near Memory (PNM)
7.1 Tesseract: Coarse-Grained Application-Level PNM Acceleration of Graph Processing
7.2 Function-Level PNM Acceleration of Mobile Consumer Workloads
7.3 Programmer-Transparent Function-Level PNM Acceleration of GPU Applications
7.4 Instruction-Level PNM Acceleration with PIM-Enabled Instructions (PEI)
7.5 Function-Level PNM Acceleration of Genome Analysis Workloads
7.6 Application-Level PNM Acceleration of Time Series Analysis
8 Enabling the Adoption of PIM
8.1 Programming Models and Code Generation for PIM
8.2 PIM Runtime: Scheduling and Data Mapping
8.3 Memory Coherence
8.4 Virtual Memory Support
8.5 Data Structures for PIM
8.6 Benchmarks and Simulation Infrastructures
8.7 Real PIM Hardware Systems and Prototypes
8.8 Security Considerations
9 Conclusion and Future Outlook
References
Neuromorphic Data Converters Using Memristors
1 Introduction
2 Motivation
2.1 Speed-Power-Accuracy Tradeoff in CMOS ADC Architectures
2.2 Figure-Of-Merit (FOM)
3 Neuromorphic Data Converters
3.1 Neural Network ADC
3.2 Neural Network DAC
3.3 Circuit Design Using Memristors
3.4 Evaluation of Neuromorphic Data Converters
4 Large-Scale Neuromorphic Mixed-Signal Data Converters
4.1 Scaling Challenges
4.2 Pipelined Neuromorphic ADC
4.3 Expanding the DAC Design
4.4 Logarithmic Neuromorphic Data Converters
4.5 Breaking Through the Speed-Power-Accuracy Tradeoff
5 Conclusions
References
Hardware Security in Emerging Photonic Network-on-Chip Architectures
1 Introduction
2 State of the Art in NoCs
3 Photonic NoCs (PNoCs) and Related Security Challenges
4 Related Work
5 Hardware Security Concerns in PNoCs
5.1 Device-Level Security Concerns
5.2 Link-Level Security Concerns
6 SOTERIA Framework: Overview
7 PV-Based Security Enhancement
8 Reservation-Assisted Security Enhancement
9 Implementing SOTERIA Framework on PNoCs
10 Evaluations
10.1 Evaluation Setup
10.2 Overhead Analysis of SOTERIA on PNoCs
10.3 Analysis of Overhead Sensitivity
11 Conclusion
References
Design Automation Flows
Synthesis and Technology Mapping for In-Memory Computing
1 Introduction
2 Background on MAGIC Operations
3 Technology Mapping Problem for MAGIC
3.1 Boolean Function Representation
3.2 Problem Definition
4 Single Row Optimal Mapping
4.1 Clauses for SAT Formulation
4.2 Determining Minimum Number of Devices
4.3 Demonstrative Example
4.4 Results
4.5 Summary
5 Delay-Constrained 2D Crossbar Mapping
5.1 LUT Graph Generation
5.2 Crossbar Mapping
5.3 Optimal Mapping Extraction
5.4 Results
5.5 Summary
6 Area-Constrained Technology Mapping Flow
6.1 LUT Placement on Crossbar
6.2 LUT Input Placement Technique
6.3 Input Alignment for Multiple LUTs
6.4 Experimental Results
6.5 Impact of Spacing Parameter
6.6 Impact of Crossbar Dimensions
6.7 Copy Overhead
6.8 Comparison with Existing Works
7 Conclusion
References
Empowering the Design of Reversible and Quantum Logic with Decision Diagrams
1 Introduction
2 Decision Diagrams for Reversible and Quantum Logic
2.1 Motivation
2.2 Compact Representation of Matrices
3 Application in the Design of Reversible and Quantum Circuits
3.1 Synthesis
3.2 Verification
3.3 Simulation
4 Conclusions
References
Error-Tolerant Mapping for Quantum Computing
1 Introduction
2 Basics of Quantum Computing
2.1 Qubits
2.2 Quantum Gates
2.3 Errors in Near-Term Quantum Processors
2.4 Mapping Challenges in Quantum Processors
3 Mapping Quantum Circuits to Quantum Processors
3.1 Reducing Swap Gates
4 Error-Tolerant Mapping of Quantum Circuits
4.1 Consideration to Gate Error
4.2 Qubit Re-allocation (QURE)
4.3 Multi-constraint Quantum Circuit Mapping
5 Error-Tolerant Mapping for Application
5.1 Background on QAOA and Impact of Noise
5.2 MaxCut
5.3 Factorization
5.4 Object Detection
6 Other Related Works and Future Outlook
6.1 Other Related Works
6.2 Future Outlook
7 Conclusion
References
System-Level Trends
Intelligent Edge Biomedical Sensors in the Internet of Things (IoT) Era
1 Introduction to Self-Aware and Adaptive Internet of Things
2 Self-Aware Machine Learning and Artificial Intelligence
2.1 Motivational Example
2.2 Centralized Two-Level Learning
2.3 Decentralized Multi-Level Learning
2.4 Case Study: Epileptic Seizure Detection
3 Self-Aware System Architecture and Platform
3.1 Platform-Aware Application Design
3.2 Patient-Aware Applications
3.3 Towards Adaptive and Multi-parametric Applications
4 Self-Aware Signal Acquisition and Sampling
4.1 When the Design Drives the Sampling: The Data Deluge
4.2 When the Signal Drives the Sampling: The Event-Driven Strategy
4.3 Evaluation of Event-Driven Sampling
5 Conclusions
References
Reconfigurable Architectures: The Shift from General Systems to Domain Specific Solutions
1 Introduction
2 Overview and Motivation
3 Towards Reconfigurable System Democratization
3.1 Design Automation Tools for FPGAs
3.2 The Abstraction Level Rise Towards Domain Specific Languages
4 Recent Trends in the Reconfigurable Systems Spotlight
4.1 Reconfigurable Computing in the Cloud: Hardware-as-a-Service
4.2 Increasing Heterogeneity in Reconfigurable Systems
4.3 Towards Domain-Specialization
5 Summary and Future Directions
References