This book constitutes the refereed proceedings of the 9th International Workshop on Architectures, Modeling, and Simulation, SAMOS 2009, held on Samos, Greece, on July 20-23, 2009.
The 18 regular papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in topical sections on architectures for multimedia, multi/many cores architectures, VLSI architectures design, architecture modeling and exploration tools.
In addition there are 14 papers from three special sessions which were organized on topics of current interest: instruction-set customization, reconfigurable computing and processor architectures, and mastering cell BE and GPU execution platforms.
Author(s): Yale Patt (auth.), Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong (eds.)
Series: Lecture Notes in Computer Science 5657 : Theoretical Computer Science and General Issues
Edition: 1
Publisher: Springer-Verlag Berlin Heidelberg
Year: 2009
Language: English
Pages: 342
Tags: Computer Hardware; Processor Architectures; Computer Communication Networks; System Performance and Evaluation; Computer System Implementation
Front Matter....Pages -
What Else Is Broken? Can We Fix It?....Pages 1-1
Programmable and Scalable Architecture for Graphics Processing Units....Pages 2-11
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors....Pages 12-23
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey....Pages 24-35
Programmable Accelerators for Reconfigurable Video Decoder....Pages 36-47
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study....Pages 48-57
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks....Pages 58-67
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC....Pages 68-77
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture....Pages 78-87
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management....Pages 88-97
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA....Pages 98-107
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing....Pages 108-117
Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata....Pages 118-127
Prediction in Dynamic SDRAM Controller Policies....Pages 128-138
Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI....Pages 139-148
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration....Pages 149-160
Modeling Scalable SIMD DSPs in LISA....Pages 161-170
NoGAP: A Micro Architecture Construction Framework....Pages 171-180
A Comparison of NoTA and GENESYS....Pages 181-192
Introduction to Instruction-Set Customization....Pages 193-193
Constraint-Driven Identification of Application Specific Instructions in the DURASE System....Pages 194-203
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)....Pages 204-214
Runtime Adaptive Extensible Embedded Processors — A Survey....Pages 215-225
Introduction to the Future of Reconfigurable Computing and Processor Architectures....Pages 226-226
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems....Pages 227-236
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study....Pages 237-246
Reconfigurable Multicore Server Processors for Low Power Operation....Pages 247-254
Reconfigurable Computing in the New Age of Parallelism....Pages 255-262
Reconfigurable Multithreading Architectures: A Survey....Pages 263-274
Introduction to Mastering Cell BE and GPU Execution Platforms....Pages 275-276
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors....Pages 277-288
Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs....Pages 289-297
Experiences with Cell-BE and GPU for Tomography....Pages 298-307
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell....Pages 308-317
Exploiting Locality on the Cell/B.E. through Bypassing....Pages 318-328
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System....Pages 329-339
Back Matter....Pages -
