This book constitutes the refereed proceedings of the 8th International Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS 2008, held in Samos, Greece, in July 2008.
The 24 revised full papers presented together with a contamplative keynote and additional papers of two special workshop sessions were carefully reviewed and selected from 62 submissions. The papers are organized in topical sections on architecture, new frontiers, SoC, application specific contributions, system level design for heterogeneous systems, programming multicores, sensors and sensor networks; and systems modeling and design.
Author(s): Mladen Berekovic, Nikitas Dimopoulos, Stephan Wong
Year: 2008
Language: English
Pages: 313
City: Berlin Heidelberg New York, NY Springer
front-matter.pdf......Page 1
Can They Be Fixed: Some Thoughts After 40 Years in the Business......Page 14
Introduction......Page 15
Connection Context Searching Revisited......Page 17
Connection Cache Approach......Page 18
Sizing of the Main Hash Table and the Cache......Page 20
References......Page 23
Introduction......Page 25
Real-Time SMT Model......Page 27
Fetch-Around Mechanism......Page 28
Experimental Framework......Page 29
Thread Performance......Page 30
Area Efficiency of the Fetch-Around Policy......Page 31
Iside Dynamic Cache Energy Consumption......Page 32
Energy Efficiency of the Fetch-Around Policy......Page 33
References......Page 34
Introduction......Page 36
Related Work......Page 37
Software Bypassing......Page 39
Experimental Setup......Page 41
Results......Page 42
References......Page 44
Introduction......Page 46
Hardware Architecture......Page 48
Technology-Independent Analysis......Page 50
AES Engine......Page 52
Conclusion......Page 53
References......Page 54
Background of QCA Nanotechnology......Page 56
Full Adder.......Page 58
Carry Lookahead Adder And Condition Sum Adder.......Page 59
Multipliers......Page 60
Serial-Parallel Multiplier.......Page 61
Array Multiplier.......Page 62
Discussion......Page 63
References......Page 64
Introduction......Page 66
Experimental Methodology......Page 68
SIMD and Cell BE Implementation of the Ssearch......Page 69
ClustalW......Page 71
Performance Results......Page 72
Analysis of Limitations......Page 75
References......Page 76
Introduction......Page 78
OFDM Framework......Page 79
Receiver......Page 80
Parameterization......Page 81
Further Changes......Page 82
Technical Results......Page 84
Development Experience......Page 85
References......Page 86
Introduction......Page 88
Related Work......Page 89
MPSoC Platform Overview......Page 90
Programming Model......Page 91
Real-Time Support......Page 92
Compiler Tool Chain......Page 93
Conclusions and Future Work......Page 96
References......Page 97
Introduction and Context......Page 98
HW/SW Mapping Performance Estimation Tools......Page 99
Closed-Formed Based Performances Estimation Tools......Page 100
Yeti......Page 101
Criteria and Degrees of Freedom......Page 102
Hierarchical Modeling......Page 103
Platform Description......Page 104
Example: Communication Network Optimization......Page 106
References......Page 107
Introduction......Page 109
Related Works......Page 110
Proposed Dual-Mode Router Micro-architecture......Page 111
Dual-Mode Router......Page 112
Performance Exploration......Page 114
Simulations Results......Page 115
Conclusions......Page 117
References......Page 118
Introduction......Page 119
PRESENT Block Cipher......Page 120
System-Level Design and Analysis Using GEZEL......Page 121
Cosimulation Based on StrongARM......Page 122
FPGA-Based Hardware/Software Co-design......Page 125
References......Page 127
Introduction......Page 129
Reed Muller Codes (RMC)......Page 130
Reed Muller Decoding......Page 131
Reliability and MTTF......Page 133
Cost Analysis......Page 135
References......Page 137
Introduction......Page 139
Erasure Iterative Decoding......Page 140
GF Instructions......Page 145
Performance Evaluation......Page 146
References......Page 147
Introduction......Page 149
Processors Featuring a Reconfigurable Accelerator......Page 150
ASIP-eFPGA Architecture......Page 151
Arithmetic Oriented eFPGA......Page 152
ASIP-eFPGA Coupling......Page 153
Arithmetic Oriented eFPGA......Page 154
Software GPS Correlator......Page 155
Results......Page 156
References......Page 158
Introduction to System Level Design for Heterogeneous Systems......Page 159
Introduction......Page 160
Streaming Architectures in FPGA......Page 161
Design Tools......Page 164
C-to-gates......Page 165
Memory Interfaces......Page 166
Implementation Platforms......Page 167
Conclusion......Page 168
References......Page 169
Introduction......Page 170
Dataflow Modeling......Page 171
Related Work......Page 172
Semantic Foundation......Page 173
Static Dataflow......Page 174
Scheduling for a Heterogeneous Application......Page 175
Design Example - Polynomial Evaluation......Page 176
Conclusions and Future Work......Page 178
References......Page 179
Introduction......Page 180
The Daedalus Design Flow......Page 181
Daedalus' Software Infrastructure......Page 182
Lessons Learned: The Tool Interoperability Problem......Page 184
Towards a Common Design Flow Infrastructure......Page 185
Related Work......Page 187
References......Page 188
Introduction......Page 190
Presentation of the Toolkit: Coware LISATek......Page 191
Sample Architecture: 32-bit RISC Processor......Page 192
Data Memory Organization......Page 193
Customized Instructions......Page 194
Experimental Results......Page 195
Synthesis Results......Page 196
Weaknesses of LISATek......Page 197
Conclusions and Future Work......Page 198
References......Page 199
Introduction......Page 200
Loop Optimization Techniques......Page 201
Principles......Page 202
Data Parallelism......Page 203
Array-OL Transformations......Page 205
Array-OL vs. Loop Transformations......Page 207
References......Page 209
Introduction......Page 210
Template Matching Algorithm......Page 211
Template Matching Modelling......Page 212
2-D Convolution Model Refinement......Page 214
Feature Extraction Model Refinement......Page 217
References......Page 219
Introduction to Programming Multicores......Page 220
Introduction......Page 221
The Hierarchical Tiled Array......Page 222
Dynamic Task Creation......Page 224
Locality vs. Load Balancing......Page 226
Execution Models......Page 227
Reference/Value Semantics......Page 228
Conclusions......Page 229
References......Page 230
Introduction......Page 231
The SVP Model and Its Resources......Page 233
Resource Negotiation in SVP......Page 235
Resource Management Protocol......Page 236
Related Work......Page 239
Summary......Page 240
References......Page 241
Introduction......Page 242
Data from Sensors......Page 243
Global Data Management......Page 245
The State-of-the-Art and the Implemented Network......Page 247
The Wireless Sensor Network (WSN)......Page 248
Conclusions......Page 249
Introduction......Page 251
Theoretical Background......Page 252
Gas Concentration Measurement in the Mid Infra Red Range......Page 255
Gas Concentration Measurement in the Ultra Violet Range......Page 256
Optical Fibre Temperature Measurement......Page 258
Conclusions......Page 259
References......Page 260
Introduction......Page 261
Related Research......Page 262
Design of TUTWSN Application Server......Page 263
Implementation of TUTWSN Application Server......Page 265
Case Application: The Weather Service......Page 267
Conclusions......Page 269
References......Page 270
Introduction......Page 271
Design Goals and Assumptions......Page 272
Diagnostics Architecture......Page 273
Diagnostics Categories......Page 274
Node Information......Page 275
Cluster and Link Traffic......Page 276
Prototype Implementation......Page 277
Memory Requirements and Communication Overhead......Page 278
Conclusions......Page 279
References......Page 280
Introduction......Page 281
Basic Analytical System Model......Page 282
Application Requirements......Page 283
Architectural Capabilities......Page 286
Analytical Performance Estimation......Page 287
Experimental Results......Page 288
Related Work......Page 289
References......Page 290
Introduction and Related Work......Page 292
The Molen Architecture......Page 293
Sesame Modeling Approach......Page 294
Application Modeling......Page 295
Architecture Modeling......Page 296
Case Study and Preliminary Results......Page 299
Conclusion and Future Work......Page 300
References......Page 301
Introduction......Page 302
Identification and Encryption......Page 304
Decryption in the Security Kernel......Page 305
Overview......Page 306
Elliptic Curve Arithmetic and Finite Field......Page 307
Encryption Performance for the C55......Page 308
Security Analysis......Page 309
Conclusions......Page 310
References......Page 311
back-matter.pdf......Page 312
