Embedded and Real-Time Operating Systems

Contents
Chapter 1: Introduction
1.1 About This Book
1.2 Motivations of This Book
1.3 Objective and Intended Audience
1.4 Unique Features of This Book
1.5 Book Contents
1.6 Use This Book as a Textbook for Embedded Systems
1.7 Use This Book as a Textbook for Operating Systems
1.8 Use This Book for Self-Study
References
Chapter 2: ARM Architecture and Programming
2.1 ARM Processor Modes
2.2 ARM CPU Registers
2.2.1 General Registers
2.2.2 Status Registers
2.2.3 Change ARM Processor Mode
2.3 Instruction Pipeline
2.4 ARM Instructions
2.4.1 Condition Flags and Conditions
2.4.2 Branch Instructions
2.4.3 Arithmetic Operations
2.4.4 Comparison Operations
2.4.5 Logical Operations
2.4.6 Data Movement Operations
2.4.7 Immediate Value and Barrel Shifter
2.4.8 Multiply Instructions
2.4.9 LOAD and Store Instructions
2.4.10 Base Register
2.4.11 Block Data Transfer
2.4.12 Stack Operations
2.4.13 Stack and Subroutines
2.4.14 Software Interrupt (SWI)
2.4.15 PSR Transfer Instructions
2.4.16 Coprocessor Instructions
2.5 ARM Toolchain
2.6 ARM System Emulators
2.7 ARM Programming
2.7.1 ARM Assembly Programming Example 1
2.7.2 ARM Assembly Programming Example 2
2.7.3 Combine Assembly with C Programming
2.7.3.1 Execution Image
2.7.3.2 Function Call Convention in C
2.7.3.3 Long Jump
2.7.3.4 Call Assembly Function from C
2.7.3.5 Call C Function from Assembly
2.7.3.6 In-Line Assembly
2.8 Device Drivers
2.8.1 System Memory Map
2.8.2 GPIO Programming
2.8.3 UART Driver for Serial I/O
2.8.3.1 Demonstration of UART Driver
2.8.3.2 Use TCP/IP Telnet Session as UART Port
2.8.4 Color LCD Display Driver
2.8.4.1 Display Image Files
2.8.4.2 Include Binary Data Sections
2.8.4.3 Programming Example C2.6: LCD Driver
2.8.4.4 Demonstration of Display Images on LCD
2.8.4.5 Display Text
2.8.4.6 Color LCD Display Driver Program
2.8.4.7 Explanations of the LCD Driver Code
2.8.4.8 Demonstration of LCD Driver Program
2.9 Summary
List of Sample Programs
Problems
References
Chapter 3: Interrupts and Exceptions Processing
3.1 ARM Exceptions
3.1.1 ARM Processor Modes
3.1.2 ARM Exceptions
3.1.3 Exceptions Vector Table
3.1.4 Exception Handlers
3.1.5 Return from Exception Handlers
3.2 Interrupts and Interrupts Processing
3.2.1 Interrupt Types
3.2.2 Interrupt Controllers
3.2.2.1 ARM PL190/192 Interrupt Controller
3.2.2.2 Vectored and Non-vectored IRQs
3.2.2.3 Interrupt Priorities
3.2.3 Primary and Secondary Interrupt Controllers
3.3 Interrupt Processing
3.3.1 Vector Table Contents
3.3.2 Hardware Interrupt Sequence
3.3.3 Interrupts Control in Software
3.3.3.1 Enable/Disable Interrupts
3.3.3.2 Interrupt Masking
3.3.3.3 Clear Device Interrupt Request
3.3.3.4 Send EOI to Vectored Interrupt Controller
3.3.4 Interrupt Handlers
3.3.4.1 Interrupt Handler Types
3.3.5 Non-nested Interrupt Handler
3.4 Timer Driver
3.4.1 ARM Versatile 926EJS Timers
3.4.2 Timer Driver Program
3.5 Keyboard Driver
3.5.1 ARM PL050 Mouse-Keyboard Interface
3.5.2 Keyboard Driver
3.5.3 Interrupt-Driven Driver Design
3.5.4 Keyboard Driver Program
3.5.5 Keyboard Driver Using Keyset 2
3.6 UART Driver
3.6.1 ARM PL011 UART Interface
3.6.2 UART Registers
3.6.3 Interrupt-Driven UART Driver Program
3.6.3.1 The uart.c File
3.6.3.2 Explanations of the UART Driver Code
3.6.3.3 Demonstration of KBD and UART Drivers
3.7 Secure Digital (SD) Cards
3.7.1 SD Card Protocols
3.7.2 SD Card Driver
3.7.3 Improved SDC Driver
3.7.4 Multi-sector Data Transfer
3.8 Vectored Interrupts
3.8.1 ARM PL190 Vectored Interrupts Controller (VIC)
3.8.2 Configure VIC for Vectored Interrupts
3.8.3 Vectored Interrupts Handlers
3.8.4 Demonstration of Vectored Interrupts
3.9 Nested Interrupts
3.9.1 Why Nested Interrupts
3.9.2 Nested Interrupts in ARM
3.9.3 Handle Nested Interrupts in SYS Mode
3.9.4 Demonstration of Nested Interrupts
3.10 Nested Interrupts and Process Switch
3.11 Summary
List of Sample Programs
Problems
References
Chapter 4: Models of Embedded Systems
4.1 Program Structures of Embedded Systems
4.2 Super-Loop Model
4.2.1 Super-Loop Program Examples
4.3 Event-Driven Model
4.3.1 Shortcomings of Super-Loop Programs
4.3.2 Events
4.3.3 Periodic Event-Driven Program
4.3.4 Asynchronous Event-Driven Program
4.4 Event Priorities
4.5 Process Models
4.5.1 Uniprocessor Process Model
4.5.2 Multiprocessor Process Model
4.5.3 Real Address Space Process Model
4.5.4 Virtual Address Space Process Model
4.5.5 Static Process Model
4.5.6 Dynamic Process Model
4.5.7 Non-preemptive Process Model
4.5.8 Preemptive Process Model
4.6 Uniprocessor (UP) Kernel Model
4.7 Uniprocessor (UP) Operating System Model
4.8 Multiprocessor (MP) System Model
4.9 Real-Time (RT) System Model
4.10 Design Methodology of Embedded System Software
4.10.1 High-Level Language Support for Event-Driven Programming
4.10.2 State Machine Model
4.10.3 StateChart Model
4.11 Summary
Problems
References
Chapter 5: Process Management in Embedded Systems
5.1 Multitasking
5.2 The Process Concept
5.3 Multitasking and Context Switch
5.3.1 A Simple Multitasking Program
5.3.2 Context Switching
5.3.3 Demonstration of Multitasking
5.4 Dynamic Processes
5.4.1 Dynamic Process Creation
5.4.2 Demonstration of Dynamic Processes
5.5 Process Scheduling
5.5.1 Process Scheduling Terminology
5.5.2 Goals, Policy, and Algorithms of Process Scheduling
5.5.3 Process Scheduling in Embedded Systems
5.6 Process Synchronization
5.6.1 Sleep and Wakeup
5.6.2 Device Drivers Using Sleep/Wakeup
5.6.2.1 Input Device Drivers
5.6.2.2 Output Device Drivers
5.7 Event-Driven Embedded Systems Using Sleep/Wakeup
5.7.1 Demonstration of Event-Driven Embedded System Using Sleep/Wakeup
5.8 Resource Management Using Sleep/Wakeup
5.8.1 Shortcomings of Sleep/Wakeup
5.9 Semaphores
5.10 Applications of Semaphores
5.10.1 Semaphore Lock
5.10.2 Mutex Lock
5.10.3 Resource Management Using Semaphore
5.10.4 Wait for Interrupts and Messages
5.10.5 Process Cooperation
5.10.5.1 Producer-Consumer Problem
5.10.5.2 Reader-Writer Problem
5.10.6 Advantages of Semaphores
5.10.7 Cautions of Using Semaphores
5.10.8 Use Semaphores in Embedded Systems
5.10.8.1 Device Drivers Using Semaphores
5.10.8.2 Event-Driven Embedded System Using Semaphore
5.11 Other Synchronization Mechanisms
5.11.1 Event Flags in OpenVMS
5.11.2 Event Variables in MVS
5.11.3 ENQ/DEQ in MVS
5.12 High-Level Synchronization Constructs
5.12.1 Condition Variables
5.12.2 Monitors
5.13 Process Communication
5.13.1 Shared Memory
5.13.2 Pipes
5.13.2.1 Pipes in Unix/Linux
5.13.2.2 Pipes in Embedded Systems
5.13.2.3 Demonstration of Pipes
5.13.3 Signals
5.13.4 Message Passing
5.13.4.1 Asynchronous Message Passing
5.13.4.2 Synchronous Message Passing
5.13.4.3 Demonstration of Message Passing
5.14 Uniprocessor (UP) Embedded System Kernel
5.14.1 Non-preemptive UP Kernel
5.14.2 Demonstration of Non-preemptive UP Kernel
5.14.3 Preemptive UP Kernel
5.14.4 Demonstration of Preemptive UP Kernel
5.15 Summary
List of Sample Programs
Problems
References
Chapter 6: Memory Management in ARM
6.1 Process Address Spaces
6.2 Memory Management Unit (MMU) in ARM
6.3 MMU Registers
6.4 Accessing MMU Registers
6.4.1 Enabling and Disabling the MMU
6.4.1.1 Enable MMU
6.4.1.2 Disable MMU
6.4.2 Domain Access Control
6.4.3 Translation Table Base Register
6.4.4 Domain Access Control Register
6.4.5 Fault Status Registers
6.4.6 Fault Address Register
6.5 Virtual Address Translations
6.5.1 Translation Table Base
6.5.2 Translation Table
6.5.3 Level-One Descriptor
6.5.3.1 Page Table Descriptor
6.5.3.2 Section Descriptor
6.6 Translation of Section References
6.7 Translation of Page References
6.7.1 Level-1 Page Table
6.7.2 Level-2 Page Descriptors
6.7.3 Translation of Small Page References
6.7.4 Translation of Large Page References
6.8 Memory Management Example Programs
6.8.1 One-Level Paging Using 1 MB Sections
6.8.2 Two-Level Paging Using 4 KB Pages
6.8.3 One-Level Paging with High VA Space
6.8.4 Two-Level Paging with High VA Space
6.8.5 Vector Table in High VA Space
6.9 Summary
List of Sample Programs
Problems
Reference
Chapter 7: User Mode Process and System Calls
7.1 User Mode Processes
7.2 Virtual Address Space Mapping
7.3 User Mode Process
7.3.1 User Mode Image
7.4 System Kernel Supporting User Mode Processes
7.4.1 PROC Structure
7.4.2 Reset Handler
7.4.2.1 Exception and IRQ Stacks
7.4.2.2 Copy Vector Table
7.4.2.3 Create Kernel Mode Page Table
7.4.2.4 Process Context Switching Function
7.4.2.5 System Call Entry and Exit
7.4.2.6 SVC Handler
7.4.2.7 Exception Handlers
7.4.3 Kernel Code
7.4.3.1 Create Process With User Mode Image
7.4.3.2 Execution of User Mode Image
7.4.4 Kernel Compile-link Script
7.4.5 Demonstration of Kernel With User Mode Process
7.5 Embedded System with User Mode Processes
7.5.1 Processes in the Same Domain
7.5.2 Demonstration of Processes in the Same Domain
7.5.3 Processes with Individual Domains
7.5.4 Demonstration of Processes with Individual Domains
7.6 RAM Disk
7.6.1 Creating RAM Disk Image
7.6.2 Process Image File Loader
7.6.3 Binary Image File Loader Program
7.7 Process Management
7.7.1 Process Creation
7.7.2 Process Termination
7.7.3 Process Family Tree
7.7.4 Wait for Child Process Termination
7.7.5 fork-exec in Unix/Linux
7.7.6 Implementation of Fork
7.7.7 Implementation of Exec
7.7.8 Demonstration of fork-exec
7.7.9 Simple sh for Command Execution
7.7.10 vfork
7.7.11 Demonstration of vfork
7.8 Threads
7.8.1 Thread Creation
7.8.2 Demonstration of Threads
7.8.3 Threads Synchronization
7.9 Embedded System with Two-level Paging
7.9.1 Static 2-level Paging
7.9.2 Demonstration of Static 2-level Paging
7.9.3 Dynamic 2-level Paging
7.9.3.1 Modifications to Kernel for Dynamic Paging
7.9.4 Demonstration of 2-level Dynamic Paging
7.10 KMH Memory Mapping
7.10.1 Remap Vector Table
7.10.2 KMH using One-level Static Paging
7.10.3 KMH Using Two-level Static Paging
7.10.4 KMH using Two-level Dynamic Paging
7.11 Embedded System Supporting File Systems
7.11.1 Create SD Card Image
7.11.2 Format SD Card Partitions as File Systems
7.11.3 Create Loop Devices for SD Card Partitions
7.12 Embedded System With SDC File System
7.12.1 SD Card Driver Using Semaphore
7.12.2 System Kernel Using SD File System
7.12.3 Demonstration of SDC File System
7.13 Boot Kernel Image from SDC
7.13.1 SDC Booter Program
7.13.2 Demonstration of Booting Kernel from SDC
7.13.3 Booting Kernel from SDC with Dynamic Paging
7.13.4 Two-Stage Booting
7.13.4.1 Stage-1 Booter
7.13.4.2 Stage-2 Booter
7.13.5 Demonstration of Two-stage Booting
7.14 Summary
List of Sample Programs
Problems
References
Chapter 8: General Purpose Embedded Operating Systems
8.1 General Purpose Operating Systems
8.2 Embedded General Purpose Operating Systems
8.3 Porting Existing GPOS to Embedded Systems
8.4 Develop an Embedded GPOS for ARM
8.5 Organization of EOS
8.5.1 Hardware Platform
8.5.2 EOS Source File Tree
8.5.3 EOS Kernel Files
8.5.4 Capabilities of EOS
8.5.5 Startup Sequence of EOS
8.5.6 Process Management in EOS
8.5.6.1 PROC and Resource Structures
8.5.7 Assembly Code of EOS
8.5.7.1 Reset Handler
8.5.7.2 Initial Page Table
8.5.7.3 System Call Entry and Exit
8.5.7.4 IRQ Handler
8.5.7.5 IRQ and Process Preemption
8.5.8 Kernel Files of EOS
8.5.8.1 The main() Function
8.5.8.2 Kernel Initialization
8.5.8.3 Process Scheduling Functions
8.5.9 Process Management Functions
8.5.9.1 fork-exec
8.5.9.2 exit-wait
8.5.10 Pipes
8.5.11 Message Passing
8.5.12 Demonstration of Message Passing
8.6 Memory Management in EOS
8.6.1 Memory Map of EOS
8.6.2 Virtual Address Spaces
8.6.3 Kernel Mode Pgdir and Page Tables
8.6.4 Process User Mode Page Tables
8.6.5 Switch Pgdir During Process Switch
8.6.6 Dynamic Paging
8.7 Exception and Signal Processing
8.7.1 Signal Processing in Unix/Linux
8.8 Signal Processing in EOS
8.8.1 Signals in PROC Resource
8.8.2 Signal Origins in EOS
8.8.3 Deliver Signal to Process
8.8.4 Change Signal Handler in Kernel
8.8.5 Signal Handling in EOS Kernel
8.8.6 Dispatch Signal Catcher for Execution in User Mode
8.9 Device Drivers
8.10 Process Scheduling in EOS
8.11 Timer Service in EOS
8.12 File System
8.12.1 File Operation Levels
8.12.2 File I/O Operations
8.12.3 EXT2 File System in EOS
8.12.3.1 File System Organization
8.12.3.2 Source Files in the EOS/FS Directory
8.12.4 Implementation of Level-1 FS
8.12.4.1 mkdir-creat-mknod
8.12.4.2 chdir-getcwd-stat
8.12.4.3 rmdir
8.12.4.4 link-unlink
8.12.4.5 symlink-readlink
8.12.4.6 Other Level-1 Functions
8.12.5 Implementation of Level-2 FS
8.12.5.1 open-close-lseek
8.12.5.2 Read Regular Files
8.12.5.3 Write Regular Files
8.12.5.4 Read-Write Special Files
8.12.5.5 Opendir-readdir
8.12.6 Implementation of Level-3 FS
8.12.6.1 mount-umount
8.12.6.2 Implications of Mount
8.12.6.3 File Protection
8.12.6.4 Real and Effective uid
8.12.6.5 File Locking
8.13 Block Device I/O Buffering
8.14 I/O Buffer Management Algorithm
8.14.1 Performance of the I/O Buffer Cache
8.15 User Interface
8.15.1 The INIT Program
8.15.2 The Login Program
8.15.3 The sh Program
8.16 Demonstration of EOS
8.16.1 EOS Startup
8.16.2 Command Processing in EOS
8.16.3 Signal and Exception Handling in EOS
8.16.3.1 Interval Timer and Alarm Signal Catcher
8.16.3.2 Exceptions Handling in EOS
8.17 Summary
Problems
References
Chapter 9: Multiprocessing in Embedded Systems
9.1 Multiprocessing
9.2 SMP System Requirements
9.3 ARM MPcore Processors
9.4 ARM Cortex-A9 MPcore Processor
9.4.1 Processor Cores
9.4.2 Snoop Control Unit (SCU)
9.4.3 Generic Interrupt Controller (GIC) [4]
9.5 GIC Programming Example
9.5.1 Configure the GIC to Route Interrupts
9.5.2 Explanations of the GIC Configuration Code
9.5.3 Interrupt Priority and Interrupt Mask
9.5.4 Demonstration of GIC Programming
9.6 Startup Sequence of ARM MPcores
9.6.1 Raw Startup Sequence
9.6.2 Booter Assisted Startup Sequence
9.6.3 SMP Booting on Virtual Machines
9.7 ARM SMP Startup Examples
9.7.1 ARM SMP Startup Example 1
9.7.2 Demonstration of SMP Startup Example 1
9.7.3 ARM SMP Startup Example 2
9.7.4 Demonstration of ARM SMP Startup Example 2
9.8 Critical Regions in SMP
9.8.1 Implementation of Critical Regions in SMP
9.8.2 Shortcomings of XCHG/SWAP Operations
9.8.3 ARM Synchronization Instructions for SMP
9.8.3.1 ARM LDREX/STREX Instructions
9.8.3.2 ARM WFI, WFE, SEV Instructions
9.8.3.3 ARM Memory Barriers
9.9 Synchronization Primitives in SMP
9.9.1 Spinlocks
9.9.2 Spinlock Example
9.9.3 Demonstration of SMP Startup with Spinlock
9.9.4 Mutex in SMP
9.9.5 Implementation of Mutex Using Spinlock
9.9.6 Demonstration of SMP Startup with Mutex Lock
9.10 Global and Local Timers
9.10.1 Demonstration of Local Timers in SMP
9.11 Semaphores in SMP
9.11.1 Applications of Semaphores in SMP
9.12 Conditional Locking
9.12.1 Conditional Spinlock
9.12.2 Conditional Mutex
9.12.3 Conditional Semaphore Operations
9.13 Memory Management in SMP
9.13.1 Memory Management Models in SMP
9.13.2 Uniform VA Spaces
9.13.2.1 Demonstration of Uniform VA Space Mapping
9.13.3 Non-uniform VA Spaces
9.13.3.1 Demonstration of Non-uniform VA Space Mapping
9.13.4 Parallel Computing in Non-uniform VA Spaces
9.14 Multitasking in SMP
9.15 SMP Kernel for Process Management
9.15.1 The ts.s file
9.15.2 The t.c file
9.15.3 Kernel.c file
9.15.4 Device Driver and Interrupt Handlers in SMP
9.15.4.1 The SDC Driver in SMP
9.15.5 Demonstration of Process Management in SMP
9.16 General Purpose SMP Operating System
9.16.1 Organization of SMP_EOS
9.16.1.1 Hardware Platform
9.16.2 SMP_EOS Source File Tree
9.16.3 SMP_EOS Kernel Files
9.16.4 Process Management in SMP_EOS
9.16.4.1 PROC Structure
9.16.4.2 Running PROC Pointers
9.16.4.3 Spinlocks and Semaphores
9.16.4.4 Use Sleep/Wakeup in SMP
9.16.5 Protect Kernel Data Structures in SMP
9.16.6 Deadlock Prevention in SMP
9.16.6.1 Deadlock Prevention in Parallel Algorithms
9.16.7 Adapt UP Algorithms for SMP
9.16.7.1 Adapt UP Process Scheduling Algorithm for SMP
9.16.7.2 Adapt UP Pipe Algorithm for SMP
9.16.7.3 Adapt UP I/O Buffer Management Algorithm for SMP
9.16.8 Device Driver and Interrupt Handlers in SMP
9.17 SMP_EOS Demonstration System
9.17.1 Startup Sequence of SMP_EOS
9.17.2 Capabilities of SMP_EOS
9.17.3 Demonstration of SMP_EOS
9.18 Summary
List of Sample Programs
Problems
References
Chapter 10: Embedded Real-Time Operating Systems
10.1 Concepts of RTOS
10.2 Task Scheduling in RTOS
10.2.1 Rate-Monotonic Scheduling (RMS)
10.2.2 Earliest-Deadline-First (EDF) Scheduling
10.2.3 Deadline-Monotonic Scheduling (DMS)
10.3 Priority Inversion
10.4 Priority Inversion Prevention
10.4.1 Priority Ceiling
10.4.2 Priority Inheritance
10.5 Survey of RTOS
10.5.1 FreeRTOS
10.5.2 MicroC/OS (μC/OS)
10.5.3 NuttX
10.5.4 VxWorks
10.5.5 QNX
10.5.6 Real-Time Linux [12]
10.5.6.1 Real-Time Linux Patches
10.5.6.2 RTLinux
10.5.7 Critique of Existing RTOS
10.5.7.1 RTOS Organizations
10.5.7.2 Tasks in RTOS
10.5.7.3 Memory Management in RTOS
Real Address Space
Virtual Address Spaces
Dynamic Memory Allocation
Stack Overflow Checking
10.5.7.4 POSIX Compliant APIs
10.5.7.5 Synchronization Primitives
10.5.7.6 Interrupts Handling in RTOS
10.5.7.7 Task Deadlines
10.6 Design Principles of RTOS
10.6.1 Interrupt Processing
10.6.2 Task Management
10.6.3 Task Scheduling
10.6.4 Synchronization Tools
10.6.5 Task Communication
10.6.6 Memory Management
10.6.7 File System
10.6.8 Tracing and Debugging
10.7 Uniprocessor RTOS (UP_RTOS)
10.7.1 Task Management in UP_RTOS
10.7.2 Task Synchronization in UP_RTOS
10.7.3 Task Scheduling in UP_RTOS
10.7.4 Task Communication in UP_RTOS
10.7.4.1 Shared Memory
10.7.4.2 Pipes for Data Streams
10.7.4.3 Message Queues
10.7.5 Protection of Critical Regions
10.7.6 File System and Logging
10.7.7 UP_RTOS with Static Periodic Tasks and Round-Robin Scheduling
10.7.8 UP_RTOS with Static Periodic Tasks and Preemptive Scheduling
10.7.9 UP_RTOS with Dynamic Tasks Sharing Resources
10.8 Multiprocessor RTOS (SMP_RTOS)
10.8.1 SMP_RTOS Kernel for Task Management
10.8.1.1 PROC Structure in SMP_RTOS
10.8.1.2 Kernel Data Structures
10.8.1.3 Protection of Kernel Data Structures
10.8.1.4 Synchronization Tools
10.8.1.5 Task Management
10.8.1.6 Demonstration of Task Management in SMP_RTOS
10.8.2 Adapt UP_RTOS to SMP
10.8.2.1 Demonstration of MP_RTOS
10.8.3 Nested Interrupts in SMP_RTOS
10.8.4 Preemptive Task Scheduling in SMP_RTOS
10.8.5 Task Switch by SGI
10.8.6 Timesliced Task Scheduling in SMP_RTOS
10.8.7 Preemptive Task Scheduling in SMP_RTOS
10.8.7.1 Reschedule Function for Task Preemption
10.8.7.2 Task Creation with Preemption
10.8.7.3 Semaphore with Preemption
10.8.7.4 Mutex with Preemption
10.8.7.5 Nested IRQ Interrupts with Preemption
10.8.8 Priority Inheritance
10.8.9 Demonstration of the SMP_RTOS System
10.9 Summary
List of Sample Programs
Problems
References
Chapter 11: ARMv8 Architecture and Programming
11.1 ARMv8 Architecture and Processors
11.1.1 Exception Levels
11.1.2 Secure World and Normal World
11.1.3 Execution States
11.1.4 Change Exception Levels
11.1.5 Change Execution States
11.2 ARMv8 Registers
11.2.1 ARMv8 Special Registers
11.2.2 Stack Pointers
11.2.3 Program Counter
11.2.4 Exception Link Registers
11.2.5 PSTATE and SPSR Registers
11.3 ARMv8 System Registers
11.4 Aarch64 Instructions
11.4.1 Data Processing Instructions
11.4.2 Shift Operations
11.4.3 Conditional Instructions
11.4.4 Memory Access Instructions
11.4.5 Flow Control Instructions
11.4.6 Exception Handling Instructions
11.4.7 Function Call Conventions in ARMv8
11.5 ARMv8 Exception and Interrupt Handling
11.5.1 Exception Types: Synchronous and Asynchronous Exceptions
11.5.2 Exception Handling
11.5.3 ARMv8 Exception Vector Table
11.5.4 Return from Exception
11.5.5 Interrupt Handling
11.5.6 A Simple Interrupt Handler
11.5.7 Nested Interrupt Handler
11.6 Generic Interrupt Controller Versions 3 and 4
11.6.1 GICv3 Fundamentals
11.6.1.1 Interrupt Types
11.6.1.2 Interrupt Identifiers
11.6.1.3 Security Model
11.6.2 Programming Model of GICv3
11.6.2.1 Distributor (GICD_*)
11.6.2.2 Redistributors (GICR_*)
11.6.2.3 CPU interfaces (ICC_*_ELn)
11.6.2.4 GICv3 Register Names
11.6.2.5 Distributor Register Map
11.6.2.6 Redistributor Register Map
11.6.2.7 CPU Interface System Registers
11.6.3 Routing in GICv3
11.6.3.1 Affinity Routing
11.6.3.2 Routing SPIs and SGIs by PE Affinity
11.6.3.3 Participating Nodes
11.6.4 Enable and Distribution of Interrupts
11.6.4.1 Enable Interrupt Groups
11.6.4.2 Enabling Individual Interrupts
11.6.5 Handling Interrupts
11.6.5.1 Interrupt Priority and Priority Mask
11.6.5.2 Interrupt Acknowledge
11.7 ARMv8 Generic Timer
11.7.1 Processor Timers
11.7.2 Counter and Frequency
11.7.3 Timer Registers
11.7.4 Configure Timer
11.7.5 Timer Interrupts
11.8 Programming Examples
11.8.1 Example 1: GICv3 in Version 2 Legacy Mode
11.8.2 Example 2: GICv3 with EL3 Physical Timer
11.8.3 Example 3: GICv3 with EL3 and EL1 Timer
11.8.4 Example 4: ARMv8 from EL3 to EL1
11.8.4.1 Changing Exception Levels
11.8.4.2 Switch from EL3 to Non-secure EL0
11.8.4.3 Example 4 Program Files
11.8.5 Example 5: OS Kernel with Processes at EL1
11.8.6 Example 6: User Mode Process and System Calls
11.8.6.1 Kernel Mode and User Mode
11.8.6.2 System Calls
11.8.6.3 Example 6 Program Code
11.8.7 Example 7: Refinement of User Mode Process
11.8.8 Example 8: Separate User Mode Image
11.9 Memory Management in ARMv8
11.9.1 Virtual Address Versus Physical Address
11.9.2 System Control Registers for MMU Operations
11.9.3 Separation of Kernel and Application Virtual Address Spaces
11.9.4 Translation Granule and Translation Tables
11.9.5 ARMv8 Translation Table Descriptor Format
11.9.6 Translation Table Descriptor Attributes
11.9.7 OS Kernel Use of Translation Table Descriptors
11.9.8 Security and the MMU
11.9.9 Context Switching in MMU
11.10 Address Translation Cases
11.10.1 4KB Page Size
11.10.2 64KB Page Size
11.10.3 64KB Page Size with 42-Bit Input VA Address
11.11 Translations in EL2 and EL3
11.12 MMU Programming Examples
11.12.1 Example 9: One-Level Table in EL3
11.12.2 Example 10: EL3 with L1 and L2 Mappings
11.12.3 Example 11: TTBR0 and TTBR1 in EL1
11.12.4 Example 12: A Simple OS Kernel with User Mode Processes
11.12.5 Example 13: OS Kernel with HIGH VA
11.13 ARMv9
11.13.1 ARMv9 for Improved Security
11.13.2 ARMv9 for Improved Computing Capability
11.14 Conclusions
References
Chapter 12: ARM TrustZone and Secure Operating Systems
12.1 ARM TrustZone Architecture
12.2 ARM TrustZone Hardware Architecture
12.2.1 Hardware Features for Secure and Normal Worlds
12.2.2 Processor Architecture
12.2.3 Switching Between Security States
12.2.4 Secure and Normal Memory Spaces
12.2.5 Secure and Normal Interrupts
12.2.6 Secure and Normal Worlds in MP Processors
12.2.7 TrustZone in ARMv8-M
12.3 TrustZone Software Architecture
12.3.1 Secure Operating System
12.3.2 Booting a Secure System
12.3.3 Software Chain of Trusts
12.3.4 Example Secure Systems
12.4 Programming Examples of Secure Systems
12.4.1 Example 12.1 Secure and Normal Worlds
12.4.2 Secure World with Interrupts
12.4.3 Programming Project
12.5 Conclusions
References
Index