Assessment runs from realizations of the extended linearization model to optimization for piecewise regular processor arrays. Emphasizes efficiency in discussions of scalable parallel-pipelined and compiled regular architectures. Also covers single chip multiprocessing for consumer electronics.
Author(s): Cirano De Dominicis, Irene Giardina
Series: Signal Processing and Communications
Edition: 1
Publisher: CRC Press, Marcel Dekker
Year: 2003
Language: English
Pages: 266
CONTENTS......Page 0
Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation......Page 1
SERIES INTRODUCTION......Page 5
PREFACE......Page 7
REFERENCES......Page 11
CONTRIBUTORS......Page 14
CONTENTS......Page 12
I. INTRODUCTION......Page 17
A. TWO’S COMPLEMENT MULTIPLIERS......Page 18
B. TRUNCATED MULTIPLIERS......Page 19
II. FIR FILTER ARCHITECTURE......Page 20
A. ARCHITECTURE OVERVIEW......Page 21
B. ARCHITECTURE COMPONENTS......Page 23
A. THE ARITHMETIC PACKAGE......Page 25
B. THE FGS PACKAGE......Page 29
IV. RESULTS......Page 30
REFERENCES......Page 32
A. GENERAL CONTEXT......Page 34
C. MADEO......Page 35
A. ARCHITECTURE MODELING......Page 36
B. PROGRAMMING CONSIDERATIONS......Page 37
C. EXECUTION MODEL......Page 39
A. FLAT EXPRESSIONS......Page 41
B. HIERARCHICAL ASPECTS......Page 43
IV. EXAMPLE OF SMALL FP MULTIPLIERS......Page 44
V. A RAID ERROR CORRECTION CASE STUDY......Page 45
A. REED–SOLOMON CODING......Page 47
B. ENCODER/DECODER SPECIFICATIONS......Page 48
C. EXPRESSION COMPILATION......Page 49
E. SPECIFIC 8:2 CASE WITH CIRCUIT GENERATION......Page 51
VI. CONCLUSION......Page 53
REFERENCES......Page 54
I. INTRODUCTION......Page 55
II. FLOWGRAPH REPRESENTATION AND PARALLEL ALGORITHMS FOR DWTS......Page 58
A. TYPE 1 CORE DWT ARCHITECTURE......Page 63
B. TYPE 2 CORE DWT ARCHITECTURE......Page 67
D. VARIABLE RESOLUTION DWT ARCHITECTURES......Page 70
IV. CONCLUSIONS AND A SUMMARY OF THE PERFORMANCE......Page 72
REFERENCES......Page 73
CHAPTER 4: STRIDE PERMUTATION ACCESS IN INTERLEAVED MEMORY SYSTEMS......Page 76
I. INTERLEAVED MEMORY SYSTEMS......Page 77
II. ACCESS SCHEME......Page 78
III. STRIDE ACCESS......Page 81
IV. STRIDE PERMUTATION ACCESS......Page 83
A. ASSUMPTIONS......Page 87
B. ACCESS SCHEME......Page 88
D. ADDRESS GENERATION......Page 91
VI. SUMMARY......Page 94
REFERENCES......Page 96
I. INTRODUCTION......Page 98
II. RELATED WORK......Page 99
III. THE SESAME MODELING AND SIMULATION ENVIRONMENT......Page 100
IV. THE SYNCHRONIZATION LAYER......Page 103
V. MODELING INTRA-TASK PARALLELISM......Page 105
VI. DATAFLOW FOR FUNCTIONAL UNIT SYNCHRONIZATION......Page 107
VII. A CASE STUDY: QR DECOMPOSITION......Page 110
A. EXPERIMENTS......Page 112
VIII. DISCUSSION......Page 115
REFERENCES......Page 116
I. INTRODUCTION......Page 119
A. ALGORITHMS......Page 120
B. SPACE-TIME MAPPING......Page 123
IV. POWER MODELING AND ENERGY ESTIMATION......Page 124
A. PE-LEVEL POWER ESTIMATION......Page 125
B. ARRAY-LEVEL POWER ESTIMATION......Page 128
V. EXPERIMENTS......Page 131
A. QUANTIFICATION OF THE POWER CONSUMPTION INSIDE ONE PROCESSOR ELEMENT......Page 132
VI. DETERMINATION OF ENERGY-OPTIMAL SPACE-TIME MAPPINGS......Page 134
VII. CONCLUSIONS AND FUTURE WORK......Page 135
REFERENCES......Page 136
I. INTRODUCTION......Page 139
II. THE MMALPHA SYSTEM......Page 141
III. THE DLMS EXAMPLE......Page 143
A. ASSUMPTIONS......Page 146
V. INTERFACE MODEL......Page 147
A. LOW-LEVEL INTERFACE AND APPLICATION INTERFACE......Page 148
A. PHASES......Page 149
B. PATTERNS......Page 150
A. GENERATING THE SOFTWARE PART......Page 153
B. GENERATING THE HARDWARE PART: PRINCIPLES......Page 155
VIII. EXPERIMENTS......Page 156
IX. RELATED WORK AND DISCUSSION......Page 158
XI. APPENDIX: VHDL CODE OF THE APPLICATION-DEPENDENT INTERFACE......Page 159
REFERENCES......Page 161
I. INTRODUCTION......Page 163
II. PROBLEM FORMULATION......Page 164
A. EVALUATION OF CONFIGURATIONS AND GOALS......Page 168
C. ACCEPTABILITY OF CONFIGURATIONS......Page 169
IV. ON-LINE CONFIGURATION MANAGEMENT......Page 171
A. ISSUES RELATED TO CONFIGURATION MANAGEMENT......Page 173
V. ON-LINE ADAPTATION......Page 176
VI. EXPERIMENTAL RESULTS......Page 178
REFERENCES......Page 181
I. INTRODUCTION......Page 183
II. IN ORDER/OUT OF ORDER CASE......Page 185
III. THE EXTENDED LINEARIZATION MODEL......Page 187
C. THE CONTROLLER (C)......Page 188
IV. REALIZATIONS OF THE EXTENDED LINEARIZATION MODEL......Page 189
V. PSEUDO-POLYNOMIAL REALIZATION......Page 190
VI. LINEAR REALIZATION......Page 191
VII. SEGMENT REALIZATION......Page 194
VIII. CAM REALIZATION......Page 196
A. GENERAL REMARKS......Page 198
B. SUMMARY......Page 200
X. CONCLUSIONS......Page 201
REFERENCES......Page 202
I. INTRODUCTION......Page 204
II. NETWORKS BROUGHT ON CHIP......Page 205
III. FROM BUSES TO NOCS......Page 208
IV. THE ÆTHEREAL APPROACH......Page 213
A. THE ÆTHEREAL CONNECTION AND TRANSACTION MODEL......Page 214
B. CONNECTION PROPERTIES......Page 217
V. CONCLUSIONS......Page 222
REFERENCES......Page 223
I. INTRODUCTION......Page 225
II. MOTIVATION......Page 226
III. ARCHITECTURE......Page 228
A. PROCESS NETWORKS......Page 230
B. IMPLEMENTATION......Page 232
V. COPROCESSOR CONTROL......Page 233
VI. CASE STUDY: PROCESS NETWORKS......Page 236
A. CODE CHANGES FOR MULTI-THREADING......Page 238
B. MEASUREMENTS......Page 240
VIII. CONCLUSIONS......Page 242
REFERENCES......Page 243
I. INTRODUCTION......Page 244
II. TRADITIONAL EMBEDDED PROCESSOR CHARACTERISTICS......Page 245
III. THE NEED FOR PROGRAMMABILITY......Page 248
IV. EARLY TIME RECONFIGURABILITY......Page 251
V. FUTURE EMBEDDED PROCESSORS......Page 253
A. REVISITING MICROCODE......Page 255
B. MICROCODED RECONFIGURABLE MOLEN EMBEDDED PROCESSOR......Page 257
C. OTHER RECONFIGURABILITY APPROACHES......Page 261
REFERENCES......Page 264
