Verilog is one of the key languages for chip layout. Not especially difficult, but you still have to somehow learn it. You can easily get manuals on Verilog, but those aren't well suited as a learning pedagogy. The attraction of this book is that it lays out [pun intended] just such a learning path. The chapters explain various aspects of the language. In toto, you get a pretty exposure to most of the language.
Plus, Verilog allows powerful simulations of chips. Necessary to reduce the cost of actually fabricating a functioning design. Another advantage of the book is that you learn how to use Verilog for design for testing, and for doing that testing.
Author(s): John Williams, Don Thomas
Edition: 1
Publisher: Springer
Year: 2008
Language: English
Pages: 399
Verilog HDL: Guide to Digital Design & Synthesis......Page 1
Contents......Page 3
Part I: Basic Verilog Topics......Page 4
1.1 Evolution of Computer Aided Digital Design......Page 6
1.2 Emergence of HDLs......Page 7
1.3 Typical Design FLow......Page 8
1.4 Importance of HDLs......Page 9
1.5 Popularity of Verilog HDL......Page 10
1.6 Trends in HDLs......Page 11
2.1 Design Methodologies......Page 14
2.2 4-bit Ripple Carry Counter......Page 16
2.3 Modules......Page 18
2.4 Instances......Page 20
2.5 Components of a Simulation......Page 21
2.6.1 Design Block......Page 23
2.6.2 Stimulus Block......Page 25
2.7 Summary......Page 27
2.8 Exercises......Page 28
3.1.1 Whitespace......Page 30
3.1.4 Number Specification......Page 31
3.1.6 Identifiers and Keywords......Page 33
3.2.1 Value Set......Page 34
3.2.2 Nets......Page 35
3.2.3 Registers......Page 36
3.2.5 Integer, Real, and Time Register Data Types......Page 37
3.2.7 Memories......Page 39
3.2.9 Strings......Page 40
3.3.1 Syatem Tasks......Page 41
3.3.2 Compiler Directives......Page 45
3.4 Summary......Page 46
3.5 Exercises......Page 47
4.1 Modules......Page 50
4.2.1 List of Ports......Page 54
4.2.2 Port Declaration......Page 55
4.2.3 Port Connecion Rules......Page 56
4.2.4 Connecting Ports to External Signals......Page 58
4.3 Hierarchical Names......Page 60
4.4 Summary......Page 61
4.5 Exercises......Page 62
5 Gate-Level Modelling......Page 64
5.1.1 And/Or Gates......Page 65
5.1.2 Buf/Not Gates......Page 67
5.1.3 Examples......Page 71
5.2.1 Rise, Fall, and Turn-off Delays......Page 79
5.2.2 Min/Typ/Max Values......Page 80
5.2.3 Delay Example......Page 82
5.3 Summary......Page 84
5.4 Exercises......Page 85
6 Dataflow Modelling......Page 88
6.1 Continuous Assigments......Page 89
6.1.1 Implicit Continuous Assignment......Page 90
6.2.1 Regular Assigment Delay......Page 91
6.2.3 Net Declaration Delay......Page 92
6.3.1 Expressions......Page 93
6.3.3 Operators......Page 94
6.4 Operator Types......Page 95
6.4.1 Arithmetic Operators......Page 96
6.4.2 Logical Operators......Page 97
6.4.3 Relational Operators......Page 98
6.4.4 Equality Operators......Page 99
6.4.5 Bitwise Operators......Page 100
6.4.6 Reduction Operators......Page 101
6.4.8 Concatenation Operator......Page 102
6.4.10 Conditional Operator......Page 103
6.4.11 Operator Precedence......Page 104
6.5.1 4-to-1 Multiplexer......Page 105
6.5.2 4-bit Full Adder......Page 107
6.5.3 Ripple Counter......Page 109
6.7 Exercises......Page 115
7 Behavioral Modelling......Page 118
7.1.1 initial Statement......Page 119
7.1.2 always Statement......Page 121
7.2.1 Blocking assigments......Page 122
7.2.2 Nonblocking Assigments......Page 123
7.3.1 Delay-Based Timing Control......Page 127
7.3.2 Event-Based Timing Control......Page 130
7.3.3 Level-Sensitive Timing Control......Page 132
7.4 Conditional Statements......Page 133
7.5 Multiway Branching......Page 134
7.5.1 case Statement......Page 135
7.5.2 casex,casez Keywords......Page 137
7.6.1 While Loop......Page 138
7.6.2 For Loop......Page 140
7.6.3 Repeat Loop......Page 141
7.6.4 Forever Loop......Page 142
7.7.1 Block Types......Page 143
7.7.2 Special Features of Blocks......Page 146
7.8.1 4-to-1 Multiplexer......Page 148
7.8.2 4-bit Counter......Page 149
7.8.3 Traffic Signal Controller......Page 150
7.9 Summary......Page 156
7.10 Exercises......Page 157
8.1 Differences Between Tasks and Fuctions......Page 160
8.2 Tasks......Page 161
8.2.1 Task Declaration and Invocation......Page 162
8.2.2 Task Examples......Page 163
8.3.1 Function Declaration and Invocation......Page 165
8.3.2 Fucntion Examples......Page 166
8.5 Exercises......Page 169
9.1.1 assign and deassign......Page 172
9.1.2 force and release......Page 174
9.2.1 defparam Statement......Page 175
9.2.2 Module_Instance Parameter Values......Page 176
9.3.1 Conditional Compilation......Page 178
9.3.2 Conditional Execution......Page 179
9.4 Time Scales......Page 180
9.5.1 File Output......Page 182
9.5.2 Dusplaying Hierarchy......Page 184
9.5.4 Random Number Generation......Page 185
9.5.5 Initializing Memory from File......Page 186
9.5.6 Value Change Dump File......Page 188
9.6 Summary......Page 189
9.7 Exercises......Page 191
Part II: Advanced Verilog Topics......Page 194
10 Timing and Delays......Page 196
10.1.1 Distributed Delays......Page 197
10.1.2 Lumped Delay......Page 198
10.1.3 Pin-to-Pin Delays......Page 199
10.2 Path Delay Modeling......Page 200
10.2.1 Specify Blocks......Page 201
10.2.2 Inside Specify Blocks......Page 202
10.3 Timing Checks......Page 208
10.3.1 $setup and $hold checks......Page 209
10.3.2 $width Check......Page 210
10.4 Delay Back-Annotation......Page 211
10.5 Summary......Page 213
10.6 Exercises......Page 214
11.1 Switch-Modeling Elements......Page 216
11.1.1 MOS Switches......Page 217
11.1.2 CMOS Switches......Page 218
11.1.3 Bidirectional Switches......Page 219
11.1.4 Power and Ground......Page 220
11.1.5 Resistive Switches......Page 221
11.1.6 Delay Specification Switches......Page 222
11.2.1 CMOS Nor Gate......Page 223
11.2.2 2-to-1 Multiplexer......Page 226
11.2.3 Simple CMOS Flip-Flop......Page 227
11.3 Summary......Page 229
11.4 Exercises......Page 230
12.1 UDP basics......Page 232
12.1.1 Parts of UDP Definition......Page 233
12.2.1 Combinational UDP Definition......Page 234
12.2.2 Stable Table Entries......Page 235
12.2.4 Instantianing UDP Primitives......Page 237
12.2.5 Example of a Combinational UDP......Page 238
12.3 Sequential UDPs......Page 241
12.3.1 Level-Sensitive Sequential UDPs......Page 242
12.3.2 Edge-Sensitive Sequential UDPs......Page 243
12.3.3 Example of a Sequential UDP......Page 245
12.4 UDP Table Shorthand Symbols......Page 247
12.5 Guidelines for UDP Design......Page 248
12.6 Summary......Page 249
12.7 Exercises......Page 250
13 Programming Language Interface......Page 252
13.1 Uses of PLI......Page 254
13.2.1 Linking PLI Tasks......Page 255
13.2.2 Invoking PLI Tasks......Page 257
13.3 Internal Data Representation......Page 258
13.4.1 Access Routines......Page 262
13.4.2 Utility Routines......Page 271
13.5 Summary......Page 275
13.6 Exercises......Page 277
14.1 What Is Logic Synthesis?......Page 278
14.2 Impact of Logic Synthesis......Page 281
14.3.1 Verilog Constructs......Page 283
14.3.2 Verilog Operators......Page 284
14.3.3 Interpretation of a Few Verilog Constructs......Page 286
14.4.1 RTL to Gates......Page 290
14.4.2 An example of RTL-to-Gates......Page 294
14.5.1 Functional Verification......Page 299
14.6.1 Verilog Coding Style......Page 302
14.6.2 Design Partitioning......Page 306
14.7.2 Circuit Requirements......Page 309
14.7.4 Verilog Description......Page 310
14.7.5 Technology Library......Page 313
14.7.8 Optimized Gate-Level Netlist......Page 314
14.7.9 Verification......Page 317
14.8 Summary......Page 319
14.9 Exercises......Page 320
Part III: Appendices......Page 322
A Stremgth Modelling and Avanced Net Definitions......Page 324
B List of PLI Routines......Page 330
C List of Keywords, System Tasks, and Compiler Directives......Page 346
D Formal Syntax Definition......Page 348
E Verilog Tidbits......Page 366
F Verilog Examples......Page 370
