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Digital Logic Testing and Simulation

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Your road map for meeting today’s digital testing challenges

Today, digital logic devices are common in products that impact public safety, including applications in transportation and human implants. Accurate testing has become more critical to reliability, safety, and the bottom line. Yet, as digital systems become more ubiquitous and complex, the challenge of testing them has become more difficult. As one development group designing a RISC stated, "the work required to . . . test a chip of this size approached the amount of effort required to design it." A valued reference for nearly two decades, Digital Logic Testing and Simulation has been significantly revised and updated for designers and test engineers who must meet this challenge.

There is no single solution to the testing problem. Organized in an easy-to-follow, sequential format, this Second Edition familiarizes the reader with the many different strategies for testing and their applications, and assesses the strengths and weaknesses of the various approaches. The book reviews the building blocks of a successful testing strategy and guides the reader on choosing the best solution for a particular application. Digital Logic Testing and Simulation, Second Edition covers such key topics as:

  • Binary Decision Diagrams (BDDs) and cycle-based simulation
  • Tester architectures/Standard Test Interface Language (STIL)
  • Practical algorithms written in a Hardware Design Language (HDL)
  • Fault tolerance
  • Behavioral Automatic Test Pattern Generation (ATPG)
  • The development of the Test Design Expert (TDX), the many obstacles encountered and lessons learned in creating this novel testing approach

Up-to-date and comprehensive, Digital Logic Testing and Simulation is an important resource for anyone charged with pinpointing faulty products and assuring quality, safety, and profitability.

Author(s): Alexander Miczo
Edition: 2
Publisher: Wiley-Interscience
Year: 2003

Language: English
Pages: 696

TeamLiB......Page 0
Cover......Page 1
Contents......Page 6
PREFACE......Page 18
1.1 INTRODUCTION......Page 24
1.3 THE TEST......Page 25
1.4 THE DESIGN PROCESS......Page 29
1.5 DESIGN AUTOMATION......Page 32
1.6 ESTIMATING YIELD......Page 34
1.7 MEASURING TEST EFFECTIVENESS......Page 37
1.8 THE ECONOMICS OF TEST......Page 43
1.9.1 The Effectiveness of Fault Simulation......Page 46
1.9.2 Evaluating Test Decisions......Page 47
1.10 SUMMARY......Page 49
PROBLEMS......Page 52
REFERENCES......Page 53
2.2 BACKGROUND......Page 56
2.3 THE SIMULATION HIERARCHY......Page 59
2.4 THE LOGIC SYMBOLS......Page 60
2.5 SEQUENTIAL CIRCUIT BEHAVIOR......Page 62
2.6 THE COMPILED SIMULATOR......Page 67
2.6.2 Sequential Circuit Simulation......Page 71
2.6.4 Hazards......Page 73
2.6.5 Hazard Detection......Page 75
2.7 EVENT- DRIVEN SIMULATION......Page 77
2.7.1 Zero- Delay Simulation......Page 79
2.7.2 Unit- Delay Simulation......Page 81
2.7.3 Nominal- Delay Simulation......Page 82
2.8 MULTIPLE- VALUED SIMULATION......Page 84
2.9.1 The Scheduler......Page 87
2.9.2 The Descriptor Cell......Page 90
2.9.3 Evaluation Techniques......Page 93
2.9.4 Race Detection in Nominal- Delay Simulation......Page 94
2.9.5 Min ¨C Max Timing......Page 95
2.10 SWITCH- LEVEL SIMULATION......Page 97
2.11.1 Introduction......Page 109
2.11.2 The Reduce Operation......Page 114
2.11.3 The Apply Operation......Page 119
2.12 CYCLE SIMULATION......Page 124
2.13 TIMING VERIFICATION......Page 129
2.13.1 Path Enumeration......Page 130
2.13.2 Block- Oriented Analysis......Page 131
2.14 SUMMARY......Page 133
PROBLEMS......Page 134
REFERENCES......Page 139
3.1 INTRODUCTION......Page 142
3.2 APPROACHES TO TESTING......Page 143
3.3.1 Analysis at the Component Level......Page 145
3.3.3 Analysis at the Gate Level......Page 147
3.4 THE STUCK- AT FAULT MODEL......Page 148
3.4.1 The AND Gate Fault Model......Page 150
3.4.4 The Tri- State Fault Model......Page 151
3.4.5 Fault Equivalence and Dominance......Page 152
3.5 THE FAULT SIMULATOR: AN OVERVIEW......Page 154
3.6.1 Parallel Fault Simulation......Page 157
3.6.2 Performance Enhancements......Page 159
3.6.3 Parallel Pattern Single Fault Propagation......Page 160
3.7.1 An Example of Concurrent Simulation......Page 162
3.7.2 The Concurrent Fault Simulation Algorithm......Page 164
3.7.3 Concurrent Fault Simulation: Further Considerations......Page 169
3.8 DELAY FAULT SIMULATION......Page 170
3.9 DIFFERENTIAL FAULT SIMULATION......Page 172
3.10 DEDUCTIVE FAULT SIMULATION......Page 174
3.11 STATISTICAL FAULT ANALYSIS......Page 175
3.12 FAULT SIMULATION PERFORMANCE......Page 178
3.13 SUMMARY......Page 180
PROBLEMS......Page 182
REFERENCES......Page 185
4.2 THE SENSITIZED PATH......Page 188
4.2.1 The Sensitized Path: An Example......Page 189
4.2.2 Analysis of the Sensitized Path Method......Page 191
4.3 THE D- ALGORITHM......Page 193
4.3.1 The D- Algorithm: An Analysis......Page 194
4.3.2 The Primitive D- Cubes of Failure......Page 197
4.3.3 Propagation D- Cubes......Page 200
4.3.4 Justification and Implication......Page 202
4.3.5 The D- Intersection......Page 203
4.4 TESTDETECT......Page 205
4.5 THE SUBSCRIPTED D- ALGORITHM......Page 207
4.6 PODEM......Page 211
4.7 FAN......Page 216
4.8 SOCRATES......Page 225
4.9 THE CRITICAL PATH......Page 228
4.10 CRITICAL PATH TRACING......Page 231
4.11 BOOLEAN DIFFERENCES......Page 233
4.12 BOOLEAN SATISFIABILITY......Page 239
4.13.1 The BDD XOR Operation......Page 242
4.13.2 Faulting the BDD Graph......Page 243
4.14 SUMMARY......Page 247
PROBLEMS......Page 249
REFERENCES......Page 253
5.2 TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC......Page 256
5.2.1 The Effects of Memory......Page 257
5.2.2 Timing Considerations......Page 260
5.3.1 Seshu¡¯s Heuristics......Page 262
5.3.2 The Iterative Test Generator......Page 264
5.3.3 The 9- Value ITG......Page 269
5.3.4 The Critical Path......Page 272
5.3.5 Extended Backtrace......Page 273
5.3.6 Sequential Path Sensitization......Page 275
5.4 SEQUENTIAL LOGIC TEST COMPLEXITY......Page 282
5.4.1 Acyclic Sequential Circuits......Page 283
5.4.2 The Balanced Acyclic Circuit......Page 285
5.4.3 The General Sequential Circuit......Page 287
5.5 EXPERIMENTS WITH SEQUENTIAL MACHINES......Page 289
5.6 A THEORETICAL LIMIT ON SEQUENTIAL TESTABILITY......Page 295
5.7 SUMMARY......Page 300
PROBLEMS......Page 301
REFERENCES......Page 303
6.1 INTRODUCTION......Page 306
6.2.1 The Static Tester......Page 307
6.2.2 The Dynamic Tester......Page 309
6.3 THE STANDARD TEST INTERFACE LANGUAGE......Page 311
6.4 USING THE TESTER......Page 316
6.5 THE ELECTRON BEAM PROBE......Page 322
6.6 MANUFACTURING TEST......Page 324
6.7 DEVELOPING A BOARD TEST STRATEGY......Page 327
6.8 THE IN- CIRCUIT TESTER......Page 330
6.9 THE PCB TESTER......Page 333
6.9.1 Emulating the Tester......Page 334
6.9.2 The Reference Tester......Page 335
6.9.3 Diagnostic Tools......Page 336
6.10 THE TEST PLAN......Page 338
6.11 VISUAL INSPECTION......Page 339
6.13 SUMMARY......Page 342
PROBLEMS......Page 343
REFERENCES......Page 344
7.2 THE TEST TRIAD......Page 346
7.3 OVERVIEW OF THE DESIGN AND TEST PROCESS......Page 348
7.4.1 The Circuit Description......Page 350
7.4.2 The Test Stimulus Description......Page 353
7.5.1 Checkpoint Faults......Page 354
7.5.2 Delay Faults......Page 356
7.5.3 Redundant Faults......Page 357
7.5.4 Bridging Faults......Page 358
7.6 TECHNOLOGY- RELATED FAULTS......Page 360
7.6.2 CMOS......Page 361
7.6.3 Fault Coverage Results in Equivalent Circuits......Page 363
7.7 THE FAULT SIMULATOR......Page 364
7.7.1 Random Patterns......Page 365
7.7.2 Seed Vectors......Page 366
7.7.3 Fault Sampling......Page 369
7.7.4 Fault- List Partitioning......Page 370
7.7.6 Iterative Fault Simulation......Page 371
7.7.8 Circuit Initialization......Page 372
7.7.9 Fault Coverage Profiles......Page 373
7.7.10 Fault Dictionaries......Page 374
7.7.11 Fault Dropping......Page 375
7.8 BEHAVIORAL FAULT MODELING......Page 376
7.8.1 Behavioral MUX......Page 377
7.8.2 Algorithmic Test Development......Page 379
7.8.3 Behavioral Fault Simulation......Page 384
7.8.4 Toggle Coverage......Page 387
7.8.5 Code Coverage......Page 388
7.9.1 Trapped Faults......Page 391
7.9.3 The Imply Operation......Page 392
7.9.4 Comprehension Versus Resolution......Page 394
7.9.6 Test Pattern Compaction......Page 395
7.9.7 Test Counting......Page 397
7.10.1 The ATPG/ Fault Simulator Link......Page 401
7.10.2 ATPG User Controls......Page 403
7.10.3 Fault- List Management......Page 404
7.11 SUMMARY......Page 405
PROBLEMS......Page 406
REFERENCES......Page 408
8.1 INTRODUCTION......Page 410
8.2 AD HOC DESIGN- FOR- TESTABILITY RULES......Page 411
8.2.1 Some Testability Problems......Page 412
8.2.2 Some Ad Hoc Solutions......Page 416
8.3.1 SCOAP......Page 419
8.3.2 Other Testability Measures......Page 426
8.3.3 Test Measure Effectiveness......Page 428
8.3.4 Using the Test Pattern Generator......Page 429
8.4.1 Overview......Page 430
8.4.2 Types of Scan- Flops......Page 433
8.4.3 Level- Sensitive Scan Design......Page 435
8.4.4 Scan Compliance......Page 439
8.4.5 Scan- Testing Circuits with Memory......Page 441
8.4.6 Implementing Scan Path......Page 443
8.5 THE PARTIAL SCAN PATH......Page 449
8.6 SCAN SOLUTIONS FOR PCBs......Page 455
8.6.1 The NAND Tree......Page 456
8.6.2 The 1149.1 Boundary Scan......Page 457
8.7 SUMMARY......Page 466
PROBLEMS......Page 467
REFERENCES......Page 472
9.1 INTRODUCTION......Page 474
9.2 BENEFITS OF BIST......Page 475
9.3 THE BASIC SELF- TEST PARADIGM......Page 477
9.3.1 A Mathematical Basis for Self- Test......Page 478
9.3.2 Implementing the LFSR......Page 482
9.3.3 The Multiple Input Signature Register ( MISR)......Page 483
9.3.4 The BILBO......Page 486
9.4.1 Determining Coverage......Page 487
9.4.2 Circuit Partitioning......Page 488
9.4.3 Weighted Random Patterns......Page 490
9.4.4 Aliasing......Page 493
9.5.1 Microprocessor- Based Signature Analysis......Page 494
9.5.2 Self- Test Using MISR/ Parallel SRSG ( STUMPS)......Page 497
9.5.3 STUMPS in the ES/ 9000 System......Page 500
9.5.4 STUMPS in the S/ 390 Microprocessor......Page 501
9.5.5 The Macrolan Chip......Page 503
9.5.6 Partial BIST......Page 505
9.6.1 The Test Controller......Page 507
9.6.2 The Desktop Management Interface......Page 510
9.7 BLACK- BOX TESTING......Page 511
9.7.1 The Ordering Relation......Page 512
9.7.2 The Microprocessor Matrix......Page 516
9.7.3 Graph Methods......Page 517
9.8 FAULT TOLERANCE......Page 518
9.8.1 Performance Monitoring......Page 519
9.8.2 Self- Checking Circuits......Page 521
9.8.3 Burst Error Correction......Page 522
9.8.4 Triple Modular Redundancy......Page 526
9.9 SUMMARY......Page 528
PROBLEMS......Page 530
REFERENCES......Page 533
10.1 INTRODUCTION......Page 536
10.2 SEMICONDUCTOR MEMORY ORGANIZATION......Page 537
10.3 MEMORY TEST PATTERNS......Page 540
10.4 MEMORY FAULTS......Page 544
10.5 MEMORY SELF- TEST......Page 547
10.5.1 A GALPAT Implementation......Page 548
10.5.2 The 9N and 13N Algorithms......Page 552
10.5.4 Parallel Test for Memories......Page 554
10.5.5 Weak Read ¨C Write......Page 556
10.6 REPAIRABLE MEMORIES......Page 558
10.7 ERROR CORRECTING CODES......Page 560
10.7.1 Vector Spaces......Page 561
10.7.2 The Hamming Codes......Page 563
10.7.3 ECC Implementation......Page 565
10.7.4 Reliability Improvements......Page 566
10.7.5 Iterated Codes......Page 568
10.8 SUMMARY......Page 569
PROBLEMS......Page 570
REFERENCES......Page 572
11.2 BACKGROUND......Page 574
11.3.1 Toggle Count......Page 576
11.3.2 The Quietest Method......Page 577
11.4 CHOOSING A THRESHOLD......Page 579
11.5 MEASURING CURRENT......Page 580
11.6 IDDQ VERSUS BURN- IN......Page 582
11.7 PROBLEMS WITH LARGE CIRCUITS......Page 585
11.8 SUMMARY......Page 587
PROBLEMS......Page 588
12.1 INTRODUCTION......Page 590
12.2 DESIGN VERIFICATION: AN OVERVIEW......Page 591
12.3.1 Performance Enhancements......Page 593
12.3.2 HDL Extensions and C++......Page 595
12.3.3 Co- design and Co- verification......Page 596
12.4.1 Coverage Evaluation......Page 598
12.4.2 Design Error Modeling......Page 601
12.5 RANDOM STIMULUS GENERATION......Page 604
12.6.1 Overview......Page 610
12.6.2 The RTL Circuit Image......Page 611
12.6.3 The Library of Parameterized Modules......Page 612
12.6.4 Some Basic Behavioral Processing Algorithms......Page 616
12.7.1 A State Traversal Problem......Page 620
12.7.2 The Petri Net......Page 625
12.8.1 An Overview of TDX......Page 630
12.8.2 DEPOT......Page 637
12.8.3 The Fault Simulator......Page 639
12.8.4 Building Goal Trees......Page 640
12.8.5 Sequential Conflicts in Goal Trees......Page 641
12.8.6 Goal Processing for a Microprocessor......Page 643
12.8.7 Bidirectional Goal Search......Page 647
12.8.8 Constraint Propagation......Page 648
12.8.9 Pitfalls When Building Goal Trees......Page 649
12.8.10 MaxGoal Versus MinGoal......Page 650
12.8.11 Functional Walk......Page 652
12.8.12 Learn Mode......Page 653
12.8.13 DFT in TDX......Page 656
12.9 DESIGN VERIFICATION......Page 658
12.9.2 Theorem Proving......Page 659
12.9.3 Equivalence Checking......Page 661
12.9.4 Model Checking......Page 663
12.9.5 Symbolic Simulation......Page 671
12.10 SUMMARY......Page 673
PROBLEMS......Page 675
INDEX......Page 680