Author(s): Gamal El-Sheikh
Series: 1
Edition: 9
Publisher: sparrow
Year: 2023
Language: English
Commentary: decrypted from 6836DA01056A27F8146E412448389648 source file
Pages: 326
City: cairo
Tags: logic design
Cairo 2023
Praise and Thanks be to ALLAH
To my wife and our daughters and sons
G.A. El-Sheikh
The Evolution of Electronic Digital Devices can be described by the following stages;
The hierarchy that clarifies the Basic Digital System Concepts including Embedded Systems Technologies is shown in (Fig. 1.1), where;
The process of Digital System Design is shown in (Fig. 1.2);
1.2 Digital Systems
Logic Conventions
Basic Characteristics
Levels of Integrated Circuits
Types of VLSI Chips
Digital Systems
Digital System Design Levels
Building binary digital solutions to computational problems;
Embedded Digital System
A Wireless Microsensor System;
Temporal Representations of Electronic Signals;
Fig. 1.14: Real Analog Signal - Bat Sonar
Digital Computer (Fig. 1.16);
Digital Computer Basic Operation;
2.1.2 Computers and Numbers
Example-2.6.6
Solution
Example-2.6.7
Solution (1)
9’s and 10’s Complement
Forming the 9’s complement
Signed Magnitude
Operations with Negative Numbers
Example-2.7.20
Example-2.7.21
Octal Subtraction
Example-2.7.22
Example-2.7.23
Example-2.7.24
Example-2.7.25
Example-2.7.26
Floating Point Representation of Real Numbers
Advantages of Binary Codes
Classifications of Binary Codes
Weighted Codes
Binary Coded Decimal (BCD) code
Advantages of BCD Codes
Disadvantages of BCD Codes
Basics
BCD in Electronics
Packed BCD
BCD Subtraction
Comparison with pure binary
Advantages
Disadvantages
Application of Gray Code
Binary to Gray Code Conversion
Gray Code to Binary Conversion
Addition of two numbers in Excess-3 Code
Decoding
Example-2.9.6
Zoned Decimal
EBCDIC zoned decimal conversion table
Background
Error Codes
Error-Detecting codes
Error-Correcting codes
Detect and Correct Errors
Parity Checking of Error Detection
Use of Parity Bit
Error Detection
Fiber Optic Transceiver
2.10.1 Binary Numbers in Electronics
2.10.2 Binary Bits of Zeros and Ones
2.10.3 Analogue Voltage Output
2.10.4 Digital Voltage Output
2.10.5 Digital Logic Levels
Digital Value Representation
TTL Input & Output Voltage Levels
Fig. 2.10.4: Digital Voltage Output Representation
Fig. 2.10.3: Analogue Voltage Output Representation
3- Logic Gates
3.1 Binary Logic
3.2 Logic Operations
3.2.1 Inversion (NOT) Operation
3.2.2 OR Operation
3.2.3 AND Operation
3.2.4 Combined OR-AND Operations
3.2.5 Truth Table
3.2.6 Symbols
3.2.7 Types of Logic Gates
The NAND and NOR gates are called universal functions since with either one the AND and OR functions and NOT (basic logic functions) can be generated. A function in sum of products (SOP) form can be implemented using NAND gates by replacing all AND an...
3.4.1 NAND gate (NAND = Not AND)
3.4.2 NOR gate (NOR = Not OR)
3.6 Combinations of Logic Gates
3.6.2 NAND gate Equivalents
The basic logic gates (NOT, AND, OR and NOR) can be realized using NAND gates as shown in the following table:
B
B (1)
F
B (2)
F (1)
B (3)
3.7 Electronics Implementation within Digital Logic Gates
3.7.1 Classification of Integrated Circuits
3.7.2 TTL and CMOS Logic Levels
Logic Levels
Ideal TTL Digital Logic Gate Voltage Levels;
3.7.3 DRL and DTL Logic Gates
3.7.4 TTL Logic Gates
TTL NOR and OR gates;
In order to turn this NOR-gate circuit into an OR-gate, we would have to invert the output logic level with another transistor stage, just like we did with the NAND-to-AND gate example. Of course, totem-pole output stages are also possible in both NOR...
3.7.5 Emitter-Coupled Digital Logic Gates
3.7.6 CMOS Gate Circuitry
3.7.7 Inverter Logic Gate
3.7.8 Static Logic Design of NAND, NOR, XOR and XNOR Gates
A static CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-down network (PDN). The function of the PUN is to provide a connection between the output and VDD anytime the output of the logic gate is meant to be 1 ...
Fig. 3.7.12: The circuit diagram for 2-input NAND, NOR, XOR and XNOR gates in CMOS static logic
3.8 Digital Logic Gates Implementation within VHDL
B (4)
4.6.1 K-mapping and Minimization Steps
Solution
Solution (1)
Solution (2)
A
B
C
D
A (1)
B (1)
C (1)
D (1)
A (2)
B (2)
C (2)
D (2)
A (3)
B (3)
B (4)
C (3)
5- Data Processing and Arithmetic Circuits
The design of logic circuits can be started with verbal description into truth tables from which the pertinent logic expressions are obtained. These logic expressions can be realized using any of the logic gates after minimization as shown in Fig. 5.0.
5.1 Comparison
5.2 Addition
5.2.3 Full Adder (FA)
Full adder using NAND or NOR logic
Full adder is a logic circuit that adds two input operand bits plus a Carry in bit and outputs a Carry out bit and a sum bit. The Sum out (Sout) of a full adder is the XOR of input operand bits A, B and the Carry in (Cin) bit. Truth table and schema...
5.2.5 Ripple Carry Adder
5.2.6 Carry Look Ahead Adder
5.3 Negative Numbers and Binary Subtraction
B
6- Combinational Circuits
6.1 Decoders
7-Segment Display Experiment
Pin connections
6.2 Encoders
Magnetic Encoder
Mechanical Encoder
Optical Encoder
War- Field -Flying Robot with a Night Vision Flying Camera
Robotic Vehicle with Metal Detector
RF based Home Automation System
Automatic Wireless Health Monitoring System
Secret Code Enabled Secure Communication
6.3 Multiplexers
6.3.1 Two-Input Multiplexer
6.3.2 Four-Input Multiplexer
6.3.3 Combined Multiplexers
References
Appendices:
Appendix-A:
Digital Principles of System Design Understanding
Appendix-B: Circuits' and Devices' Symbols
Appendix-C:
Electronic Devices and Circuits: Significant Equations
Appendix-D:
Laboratory Experiments and Assignments
Lab-04: Inverters
E.1 Integrated Circuits Functioning
Notes
E.2 Integrated Circuits Pin Configuration
F.1 Integrated Circuits Functioning
The following is a list of CMOS 4000 series digital logic integrated circuits that represent Logic Gates. The 4000-series CMOS logic circuits include several integrated circuits (ICs) that provide several electronic logic gates in a single package. Ea...
F.2 Integrated Circuits Pin Configuration