Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design. ·Unique presentation of digital logic design from the perspective of computer architecture using a real instruction set, MIPS.·Side-by-side examples of the two most prominent Hardware Design Languages--VHDL and Verilog--illustrate and compare the ways the each can be used in the design of digital systems.·Worked examples conclude each section to enhance the reader's understanding and retention of the material.·Companion Web site includes links to CAD tools for FPGA design from Synplicity and Xilinx,lecture slides, laboratory projects, and solutions to exercises.
Author(s): David Harris, Sarah Harris
Year: 2007
Language: English
Pages: 593
In Praise of Digital Design and Computer Architecture......Page 2
About the Authors......Page 5
Title page......Page 6
Copyright page......Page 7
Contents
......Page 10
Preface......Page 18
FEATURES......Page 19
Xilinx ISE WebPACK......Page 20
LABS......Page 21
ACKNOWLEDGMENTS......Page 22
1.1 THE GAME PLAN......Page 26
1.2.1 Abstraction......Page 27
1.2.2 Discipline......Page 28
1.2.3 The Three -Y’s......Page 29
1.3 THE DIGITAL ABSTRACTION......Page 30
1.4.2 Binary Numbers......Page 32
1.4.3 Hexadecimal Numbers......Page 34
1.4.4 Bytes, Nibbles, and All That Jazz......Page 36
1.4.5 Binary Addition......Page 37
1.4.6 Signed Binary Numbers......Page 38
1.5 LOGIC GATES......Page 42
1.5.3 AND Gate......Page 43
1.5.6 Multiple-Input Gates......Page 44
1.6.2 Logic Levels......Page 45
1.6.4 DC Transfer Characteristics......Page 46
1.6.5 The Static Discipline......Page 47
1.7 CMOS TRANSISTORS......Page 49
1.7.2 Diodes......Page 50
1.7.4 nMOS and pMOS Transistors......Page 51
1.7.6 Other CMOS Logic Gates......Page 54
1.7.8 Pseudo-nMOS Logic......Page 56
1.8 POWER CONSUMPTION......Page 57
1.9 SUMMARY AND A LOOK AHEAD......Page 58
Exercises......Page 60
Interview Questions......Page 71
2.1 INTRODUCTION......Page 74
2.2.2 Sum-of-Products Form......Page 77
2.3 BOOLEAN ALGEBRA......Page 79
2.3.2 Theorems of One Variable......Page 80
2.3.3 Theorems of Several Variables......Page 81
2.3.4 The Truth Behind It All......Page 83
2.3.5 Simplifying Equations......Page 84
2.4 FROM LOGIC TO GATES......Page 85
2.5 MULTILEVEL COMBINATIONAL LOGIC......Page 88
2.5.1 Hardware Reduction......Page 89
2.5.2 Bubble Pushing......Page 90
2.6.1 Illegal Value: X......Page 92
2.6.2 Floating Value: Z......Page 93
2.7 KARNAUGH MAPS......Page 94
2.7.1 Circular Thinking......Page 95
2.7.2 Logic Minimization with K-Maps......Page 96
2.7.3 Don’t Cares......Page 100
2.7.4 The Big Picture......Page 101
2.8.1 Multiplexers......Page 102
2.8.2 Decoders......Page 105
2.9.1 Propagation and Contamination Delay......Page 107
2.9.2 Glitches......Page 111
2.10 SUMMARY......Page 114
Exercises......Page 116
Interview Questions......Page 123
3.2 LATCHES AND FLIP-FLOPS......Page 126
3.2.1 SR Latch......Page 128
3.2.2 D Latch......Page 130
3.2.4 Register......Page 131
3.2.5 Enabled Flip-Flop......Page 132
3.2.7 Transistor-Level Latch and Flip-Flop Designs......Page 133
3.2.8 Putting It All Together......Page 135
3.3.1 Some Problematic Circuits......Page 136
3.3.2 Synchronous Sequential Circuits......Page 137
3.3.3 Synchronous and Asynchronous Circuits......Page 139
3.4.1 FSM Design Example......Page 140
3.4.2 State Encodings......Page 146
3.4.3 Moore and Mealy Machines......Page 149
3.4.4 Factoring State Machines......Page 152
3.4.5 FSM Review......Page 155
3.5 TIMING OF SEQUENTIAL LOGIC......Page 156
3.5.1 The Dynamic Discipline......Page 157
3.5.2 System Timing......Page 158
3.5.3 Clock Skew......Page 163
3.5.4 Metastability......Page 166
3.5.5 Synchronizers......Page 167
3.5.6 Derivation of Resolution Time......Page 169
3.6 PARALLELISM......Page 172
3.7 SUMMARY......Page 176
Exercises......Page 178
Untitled......Page 188
4.1.1 Modules......Page 190
4.1.2 Language Origins......Page 191
4.1.3 Simulation and Synthesis......Page 192
4.2.1 Bitwise Operators......Page 194
4.2.2 Comments and White Space......Page 197
4.2.4 Conditional Assignment......Page 198
4.2.5 Internal Variables......Page 199
4.2.6 Precedence......Page 201
4.2.8 Z’s and X’s......Page 202
4.2.10 Delays......Page 205
4.2.11 VHDL Libraries and Types......Page 206
4.3 STRUCTURAL MODELING......Page 208
4.4.1 Registers......Page 213
4.4.2 Resettable Registers......Page 214
4.4.3 Enabled Registers......Page 216
4.4.4 Multiple Registers......Page 217
4.5 MORE COMBINATIONAL LOGIC......Page 218
4.5.1 Case Statements......Page 221
4.5.2 If Statements......Page 222
4.5.4 Blocking and Nonblocking Assignments......Page 224
4.6 FINITE STATE MACHINES......Page 229
4.7 PARAMETERIZED MODULES......Page 234
4.8 TESTBENCHES......Page 237
4.9 SUMMARY......Page 241
Exercises......Page 242
Verilog Exercises......Page 247
VHDL Exercises......Page 250
Interview Questions......Page 253
5.2.1 Addition......Page 256
5.2.3 Comparators......Page 263
5.2.4 ALU......Page 265
5.2.5 Shifters and Rotators......Page 267
5.2.6 Multiplication......Page 269
5.2.7 Division......Page 270
5.2.8 Further Reading......Page 271
5.3.1 Fixed-Point Number Systems......Page 272
5.3.2 Floating-Point Number Systems......Page 273
5.4.1 Counters......Page 277
5.4.2 Shift Registers......Page 278
5.5.1 Overview......Page 280
5.5.3 Static Random Access Memory (SRAM)......Page 283
5.5.5 Register Files......Page 284
5.5.6 Read Only Memory......Page 285
5.5.8 Memory HDL......Page 287
5.6.1 Programmable Logic Array......Page 289
5.6.2 Field Programmable Gate Array......Page 291
5.6.3 Array Implementations......Page 296
5.7 SUMMARY......Page 297
Exercises......Page 299
Interview Questions......Page 309
6.1 INTRODUCTION......Page 312
6.2.1 Instructions......Page 313
6.2.2 Operands: Registers, Memory, and Constants......Page 315
6.3.1 R-type Instructions......Page 322
6.3.2 I-Type Instructions......Page 324
6.3.4 Interpreting Machine Language Code......Page 325
6.3.5 The Power of the Stored Program......Page 326
6.4.1 Arithmetic/Logical Instructions......Page 327
6.4.2 Branching......Page 331
6.4.3 Conditional Statements......Page 333
6.4.4 Getting Loopy......Page 334
6.4.5 Arrays......Page 337
6.4.6 Procedure Calls......Page 342
6.5 ADDRESSING MODES......Page 350
6.6.1 The Memory Map......Page 353
6.6.2 Translating and Starting a Program......Page 354
6.7.1 Pseudoinstructions......Page 359
6.7.2 Exceptions......Page 360
6.7.3 Signed and Unsigned Instructions......Page 361
6.7.4 Floating-Point Instructions......Page 363
6.8 REAL-WORLD PERSPECTIVE: IA-32 ARCHITECTURE......Page 364
6.8.2 IA-32 Operands......Page 365
6.8.4 IA-32 Instructions......Page 367
6.8.5 IA-32 Instruction Encoding......Page 369
6.8.6 Other IA-32 Peculiarities......Page 371
6.9 SUMMARY......Page 372
Exercises......Page 374
Interview Questions......Page 384
7.1.1 Architectural State and Instruction Set......Page 386
7.1.2 Design Process......Page 387
7.2 PERFORMANCE ANALYSIS......Page 389
7.3.1 Single-Cycle Datapath......Page 391
7.3.2 Single-Cycle Control......Page 397
7.3.3 More Instructions......Page 400
7.3.4 Performance Analysis......Page 403
7.4 MULTICYCLE PROCESSOR......Page 404
7.4.1 Multicycle Datapath......Page 405
7.4.2 Multicycle Control......Page 411
7.4.3 More Instructions......Page 418
7.4.4 Performance Analysis......Page 420
7.5 PIPELINED PROCESSOR......Page 424
7.5.1 Pipelined Datapath......Page 427
7.5.2 Pipelined Control......Page 428
7.5.3 Hazards......Page 429
7.5.5 Performance Analysis......Page 441
7.6 HDL REPRESENTATION......Page 444
7.6.1 Single-Cycle Processor......Page 445
7.6.2 Generic Building Blocks......Page 449
7.6.3 Testbench......Page 451
7.7 EXCEPTIONS......Page 454
7.8.1 Deep Pipelines......Page 458
7.8.2 Branch Prediction......Page 460
7.8.3 Superscalar Processor......Page 461
7.8.4 Out-of-Order Processor......Page 464
7.8.5 Register Renaming......Page 466
7.8.6 Single Instruction Multiple Data......Page 468
7.8.7 Multithreading......Page 469
7.9 REAL-WORLD PERSPECTIVE: IA-32 MICROARCHITECTURE......Page 470
7.10 SUMMARY......Page 476
Exercises......Page 478
Untitled......Page 484
8.1 INTRODUCTION......Page 486
8.2 MEMORY SYSTEM PERFORMANCE ANALYSIS......Page 490
8.3 CACHES......Page 491
8.3.1 What Data Is Held in the Cache?......Page 492
8.3.2 How Is the Data Found?......Page 493
8.3.3 What Data Is Replaced?......Page 501
8.3.4 Advanced Cache Design......Page 502
8.3.5 The Evolution of MIPS Caches......Page 506
8.4 VIRTUAL MEMORY......Page 507
8.4.1 Address Translation......Page 509
8.4.2 The Page Table......Page 511
8.4.3 The Translation Lookaside Buffer......Page 513
8.4.4 Memory Protection......Page 514
8.4.6 Multilevel Page Tables......Page 515
8.5 MEMORY-MAPPED I/O......Page 517
8.6.1 IA-32 Cache Systems......Page 522
8.6.2 IA-32 Virtual Memory......Page 524
8.7 SUMMARY......Page 525
EPILOGUE......Page 526
Exercises......Page 527
Interview Questions......Page 535
A.2 74XX LOGIC......Page 538
A.3.1 PROMs......Page 539
A.3.2 PLAs......Page 543
A.3.3 FPGAs......Page 544
A.5 DATA SHEETS......Page 546
A.6 LOGIC FAMILIES......Page 552
A.7 PACKAGING AND ASSEMBLY......Page 554
A.8 TRANSMISSION LINES......Page 557
A.8.1 Matched Termination......Page 559
A.8.2 Open Termination......Page 561
A.8.4 Mismatched Termination......Page 562
A.8.6 Proper Transmission Line Terminations......Page 565
A.8.7 Derivation of Z0......Page 567
A.8.8 Derivation of the Reflection Coefficient......Page 568
A.8.9 Putting It All Together......Page 569
A.9 ECONOMICS......Page 570
Appendix B MIPS Instructions......Page 574
Further Reading......Page 578
Index......Page 580
