Digital Design and Computer Architecture: ARM Edition

Front Cover
Digital Design and Computer Architecture
Copyright Page
Contents
Preface
Features
Side-by-Side Coverage of SystemVerilog and VHDL
ARM Architecture and Microarchitecture
Real-World Perspectives
Accessible Overview of Advanced Microarchitecture
End-of-Chapter Exercises and Interview Questions
Online Supplements
How To Use The Software Tools In A Course
Altera Quartus II
Keil's ARM Microcontroller Development Kit (MDK-ARM)
Labs
Bugs
Acknowledgments
1 From Zero to One
1.1 The Game Plan
1.2 The Art of Managing Complexity
1.2.1 Abstraction
1.2.2 Discipline
1.2.3 The Three-Y's
1.3 The Digital Abstraction
1.4 Number Systems
1.4.1 Decimal Numbers
1.4.2 Binary Numbers
1.4.3 Hexadecimal Numbers
1.4.4 Bytes, Nibbles, and All That Jazz
1.4.5 Binary Addition
1.4.6 Signed Binary Numbers
Sign/Magnitude Numbers
Two's Complement Numbers
Comparison of Number Systems
1.5 Logic Gates
1.5.1 NOT Gate
1.5.2 Buffer
1.5.3 AND Gate
1.5.4 OR Gate
1.5.5 Other Two-Input Gates
1.5.6 Multiple-Input Gates
1.6 Beneath the Digital Abstraction
1.6.1 Supply Voltage
1.6.2 Logic Levels
1.6.3 Noise Margins
1.6.4 DC Transfer Characteristics
1.6.5 The Static Discipline
1.7 CMOS Transistors
1.7.1 Semiconductors
1.7.2 Diodes
1.7.3 Capacitors
1.7.4 nMOS and pMOS Transistors
1.7.5 CMOS NOT Gate
1.7.6 Other CMOS Logic Gates
1.7.7 Transmission Gates
1.7.8 Pseudo-nMOS Logic
1.8 Power Consumption
1.9 Summary and a Look Ahead
Exercises
Interview Questions
2 Combinational Logic Design
2.1 Introduction
2.2 Boolean Equations
2.2.1 Terminology
2.2.2 Sum-of-Products Form
2.2.3 Product-of-Sums Form
2.3 Boolean Algebra
2.3.1 Axioms
2.3.2 Theorems of One Variable
2.3.3 Theorems of Several Variables
2.3.4 The Truth Behind It All
2.3.5 Simplifying Equations
2.4 From Logic to Gates
2.5 Multilevel Combinational Logic
2.5.1 Hardware Reduction
2.5.2 Bubble Pushing
2.6 X’s and Z’s, Oh My
2.6.1 Illegal Value: X
2.6.2 Floating Value: Z
2.7 Karnaugh Maps
2.7.1 Circular Thinking
2.7.2 Logic Minimization with K-Maps
2.7.3 Don't Cares
2.7.4 The Big Picture
2.8 Combinational Building Blocks
2.8.1 Multiplexers
2.8.2 Decoders
2.9 Timing
2.9.1 Propagation and Contamination Delay
2.9.2 Glitches
2.10 Summary
Exercises
Interview Questions
3 Sequential Logic Design
3.1 Introduction
3.2 Latches and Flip-Flops
3.2.1 SR Latch
3.2.2 D Latch
3.2.3 D FIip-Flop
3.2.4 Register
3.2.5 Enabled Flip-Flop
3.2.6 Resettable Flip-Flop
3.2.7 Transistor-Level Latch and Flip-Flop Designs
3.2.8 Putting It All Together
3.3 Synchronous Logic Design
3.3.1 Some Problematic Circuits
3.3.2 Synchronous Sequential Circuits
3.3.3 Synchronous and Asynchronous Circuits
3.4 Finite State Machines
3.4.1 FSM Design Example
3.4.2 State Encodings
3.4.3 Moore and Mealy Machines
3.4.4 Factoring State Machines
3.4.5 Deriving an FSM from a Schematic
3.4.6 FSM Review
3.5 Timing of Sequential Logic
3.5.1 The Dynamic Discipline
3.5.2 System Timing
3.5.3 Clock Skew
3.5.4 Metastability
3.5.5 Synchronizers
3.5.6 Derivation of Resolution Time
3.6 Parallelism
3.7 Summary
Exercises
Interview Questions
4 Hardware Description Languages
4.1 Introduction
4.1.1 Modules
4.1.2 Language Origins
4.1.3 Simulation and Synthesis
4.2 Combinational Logic
4.2.1 Bitwise Operators
4.2.2 Comments and White Space
4.2.3 Reduction Operators
4.2.4 Conditional Assignment
4.2.5 Internal Variables
4.2.6 Precedence
4.2.7 Numbers
4.2.8 Z’s and X’s
4.2.9 Bit Swizzling
4.2.10 Delays
4.3 Structural Modeling
4.4 Sequential Logic
4.4.1 Registers
4.4.2 Resettable Registers
4.4.3 Enabled Registers
4.4.4 Multiple Registers
4.4.5 Latches
4.5 More Combinational Logic
4.5.1 Case Statements
4.5.2 If Statements
4.5.3 Truth Tables with Don’t Cares
4.5.4 Blocking and Nonblocking Assignments
4.6 Finite State Machines
4.7 Data Types
4.7.1 SystemVerilog
4.7.2 VHDL
4.8 Parameterized Modules
4.9 Testbenches
4.10 Summary
Exercises
Interview Questions
5 Digital Building Blocks
5.1 Introduction
5.2 Arithmetic Circuits
5.2.1 Addition
Half Adder
Full Adder
Carry Propagate Adder
Ripple-Carry Adder
Carry-Lookahead Adder
Prefix Adder
Putting It All Together
5.2.2 Subtraction
5.2.3 Comparators
5.2.4 ALU
5.2.5 Shifters and Rotators
5.2.6 Multiplication
5.2.7 Division
5.2.8 Further Reading
5.3 Number Systems
5.3.1 Fixed-Point Number Systems
5.3.2 Floating-Point Number Systems
Special Cases: 0, ±∞, and NaN
Single- and Double-Precision Formats
Rounding
Floating-Point Addition
5.4 Sequential Building Blocks
5.4.1 Counters
5.4.2 Shift Registers
5.5 Memory Arrays
5.5.1 Overview
Bit Cells
Organization
Memory Ports
Memory Types
5.5.2 Dynamic Random Access Memory (DRAM)
5.5.3 Static Random Access Memory (SRAM)
5.5.4 Area and Delay
5.5.5 Register Files
5.5.6 Read Only Memory
5.5.7 Logic Using Memory Arrays
5.5.8 Memory HDL
5.6 Logic Arrays
5.6.1 Programmable Logic Array
5.6.2 Field Programmable Gate Array
5.6.3 Array Implementations
5.7 Summary
Exercises
Interview Questions
6 Architecture
6.1 Introduction
6.2 Assembly Language
6.2.1 Instructions
6.2.2 Operands: Registers, Memory, and Constants
Registers
The Register Set
Constants/Immediates
Memory
6.3 Programming
6.3.1 Data-processing Instructions
Logical Instructions
Shift Instructions
Multiply Instructions*
6.3.2 Condition Flags
6.3.3 Branching
6.3.4 Conditional Statements
if Statements
if/else Statements
switch/case Statements*
6.3.5 Getting Loopy
while Loops
for Loops
6.3.6 Memory
Bytes and Characters
6.3.7 Function Calls
Function Calls and Returns
Input Arguments and Return Values
The Stack
Loading and Storing Multiple Registers
Preserved Registers
Nonleaf Function Calls
Recursive Function Calls
Additional Arguments and Local Variables*
6.4 Machine Language
6.4.1 Data-processing Instructions
6.4.2 Memory Instructions
6.4.3 Branch Instructions
6.4.4 Addressing Modes
6.4.5 Interpreting Machine Language Code
6.4.6 The Power of the Stored Program
6.5 Lights, Camera, Action: Compiling, Assembling, and Loading
6.5.1 The Memory Map
The Text Segment
The Global Data Segment
The Dynamic Data Segment
The Exception Handler, OS, and I/O Segments
6.5.2 Compilation
6.5.3 Assembling
6.5.4 Linking
6.5.5 Loading
6.6 Odds and Ends
6.6.1 Loading Literals
6.6.2 NOP
6.6.3 Exceptions
Execution Modes and Privilege Levels
Exception Vector Table
Banked Registers
Exception Handling
Exception-Related Instructions
Start-up
6.7 Evolution of ARM Architecture
6.7.1 Thumb Instruction Set
6.7.2 DSP Instructions
6.7.3 Floating-Point Instructions
6.7.4 Power-Saving and Security Instructions
6.7.5 SIMD Instructions
6.7.6 64-bit Architecture
6.8 Another Perspective: x86 Architecture
6.8.1 x86 Registers
6.8.2 x86 Operands
6.8.3 Status Flags
6.8.4 x86 Instructions
6.8.5 x86 Instruction Encoding
6.8.6 Other x86 Peculiarities
6.8.7 The Big Picture
6.9 Summary
Exercises
Interview Questions
7 Microarchitecture
7.1 Introduction
7.1.1 Architectural State and Instruction Set
7.1.2 Design Process
7.1.3 Microarchitectures
7.2 Performance Analysis
7.3 Single-Cycle Processor
7.3.1 Single-Cycle Datapath
7.3.2 Single-Cycle Control
7.3.3 More Instructions
7.3.4 Performance Analysis
7.4 Multicycle Processor
7.4.1 Multicycle Datapath
LDR
STR
Data-Processing Instructions with Immediate Addressing
7.4.2 Multicycle Control
7.4.3 Performance Analysis
7.5 Pipelined Processor
7.5.1 Pipelined Datapath
7.5.2 Pipelined Control
7.5.3 Hazards
7.5.4 Performance Analysis
7.6 HDL Representation
7.6.1 Single-Cycle Processor
7.6.2 Generic Building Blocks
7.6.3 Testbench
7.7 Advanced Microarchitecture
7.7.1 Deep Pipelines
7.7.2 Micro-Operations
7.7.3 Branch Prediction
7.7.4 Superscalar Processor
7.7.5 Out-of-Order Processor
7.7.6 Register Renaming
7.7.7 Multithreading
7.7.8 Multiprocessors
7.8 Real-World Perspective: Evolution of ARM Microarchitecture
7.9 Summary
Exercises
Interview Questions
8 Memory Systems
8.1 Introduction
8.2 Memory System Performance Analysis
8.3 Caches
8.3.1 What Data is Held in the Cache?
8.3.2 How is Data Found?
Direct Mapped Cache
Multi-way Set Associative Cache
Fully Associative Cache
Block Size
Putting it All Together
8.3.3 What Data is Replaced?
8.3.4 Advanced Cache Design
Multiple-Level Caches
Reducing Miss Rate
Write Policy
8.3.5 The Evolution of ARM Caches
8.4 Virtual Memory
8.4.1 Address Translation
8.4.2 The Page Table
8.4.3 The Translation Lookaside Buffer
8.4.4 Memory Protection
8.4.5 Replacement Policies
8.4.6 Multilevel Page Tables
8.5 Summary
Epilogue
Exercises
Interview Questions
9 I/O Systems
9.1 Introduction
9.2 Memory-Mapped I/O
9.3 Embedded I/O Systems
9.3.1 BCM2835 System-on-Chip
9.3.2 Device Drivers
9.3.3 General-Purpose Digital I/O
9.3.4 Serial I/O
9.3.4.1 Serial Peripheral Interface (SPI)
9.3.4.2 Universal Asynchronous Receiver/Transmitter (UART)
9.3.5 Timers
9.3.6 Analog I/O
9.3.6.1 D/A Conversion
9.3.6.2 Pulse-Width Modulation
9.3.6.3 A/D Conversion
9.3.7 Interrupts
9.4 Other Microcontroller Peripherals
9.4.1 Character LCDs
9.4.2 VGA Monitor
9.4.3 Bluetooth Wireless Communication
9.4.4 Motor Control
9.4.4.1 DC Motors
9.4.4.2 Servo Motor
9.4.4.3 Stepper Motor
9.5 Bus Interfaces
9.5.1 AHB-Lite
9.5.2 Memory and Peripheral Interface Example
9.6 PC I/O Systems
9.6.1 USB
9.6.2 PCI and PCI Express
9.6.3 DDR3 Memory
9.6.4 Networking
9.6.5 SATA
9.6.6 Interfacing to a PC
9.6.6.1 Data Acquisition Systems
9.6.6.2 USB Links
9.7 Summary
Appendix A Digital System Implementation
A.1 Introduction
A.2 74xx Logic
A.2.1 Logic Gates
A.2.2 Other Functions
A.3 Programmable Logic
A.3.1 PROMs
A.3.2 PLAs
A.3.3 FPGAs
A.4 Application-Specific Integrated Circuits
A.5 Data Sheets
A.6 Logic Families
A.7 Packaging and Assembly
A.8 Transmission Lines
A.8.1 Matched Termination
A.8.2 Open Termination
A.8.3 Short Termination
A.8.4 Mismatched Termination
A.8.5 When to Use Transmission Line Models
A.8.6 Proper Transmission Line Terminations
A.8.7 Derivation of Z0
A.8.8 Derivation of the Reflection Coefficient
A.8.9 Putting It All Together
A.9 Economics
Appendix B ARM Instructions
B.1 Data-Processing Instructions
B.1.1 Multiply Instructions
B.2 Memory Instructions
B.3 Branch Instructions
B.4 Miscellaneous Instructions
B.5 Condition Flags
Appendix C C Programming
C.1 Introduction
C.2 Welcome to C
C.2.1 C Program Dissection
C.2.2 Running a C Program
C.3 Compilation
C.3.1 Comments
C.3.2 #define
C.3.3 #include
C.4 Variables
C.4.1 Primitive Data Types
C.4.2 Global and Local Variables
C.4.3 Initializing Variables
C.5 Operators
C.6 Function Calls
C.7 Control-Flow Statements
C.7.1 Conditional Statements
C.7.2 Loops
C.8 More Data Types
C.8.1 Pointers
C.8.2 Arrays
C.8.3 Characters
C.8.4 Strings
C.8.5 Structures
C.8.6 typedef
C.8.7 Dynamic Memory Allocation
C.8.8 Linked Lists
C.9 Standard Libraries
C.9.1 stdio
C.9.2 stdlib
C.9.3 math
C.9.4 string
C.10 Compiler and Command Line Options
C.10.1 Compiling Multiple C Source Files
C.10.2 Compiler Options
C.10.3 Command Line Arguments
C.11 Common Mistakes
Index