This book provides an overview of emerging semiconductor devices and their applications in electronic circuits, which form the foundation of electronic devices. Device Circuit Co-Design Issues in FETs provides readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The book brings researchers and engineers from various disciplines of the VLSI domain together to tackle the emerging challenges in the field of engineering and applications of advanced low-power devices in an effort to improve the performance of these technologies. The chapters examine the challenges and scope of FinFET device circuits, 3D FETs, and advanced FET for circuit applications. The book also discusses low-power memory design, neuromorphic computing, and issues related to thermal reliability. The authors provide a good understanding of device physics and circuits, and discuss transistors based on the new channel/dielectric materials and device architectures to achieve low-power dissipation and ultra-high switching speeds to fulfill the requirements of the semiconductor industry.
This book is intended for students, researchers, and professionals in the field of semiconductor devices and nanodevices, as well as those working on device-circuit co-design issues.
Author(s): Shubham Tayal, Billel Smaani, Shiromani Balmukund Rahi, Samir Labiod, Zeinab Ramezani
Series: Materials, Devices, and Circuits
Publisher: CRC Press
Year: 2023
Language: English
Pages: 279
City: Boca Raton
Cover
Half Title
Series Page
Title Page
Copyright Page
Table of Contents
Preface
Editor biographies
Contributors
Chapter 1 Modeling for CMOS circuit design
1.1 CMOS devices
1.1.1 Introduction
1.1.2 Switch of CMOS
1.1.3 The implementation and operation of the CMOS inverter
1.2 The CMOS IC design process
1.2.1 Background
1.2.2 CMOS inverter characteristics
1.3 The logic circuit of CMOS
1.3.1 The inverter
1.3.1.1 Overview
1.3.1.2 Simulation
1.3.2 CMOS NAND gate
1.3.2.1 Overview
1.3.2.2 Simulation
1.3.3 CMOS NOR gate
1.3.3.1 Overview
1.3.3.2 Simulation
1.4 CMOS technology and applications
1.5 Layout of CMOS
1.6 Conclusion
References
Chapter 2 Conventional CMOS circuit design
2.1 Introduction
2.2 CMOS fabrication technology
2.2.1 Well formation
2.2.2 MOSFET fabrication process
2.2.3 Interconnections
2.2.4 Layout of MOS transistor
2.2.5 Long and short-channel MOSFETs
2.3 Parasitics associated with CMOS technology
2.3.1 RC delay through the n-well
2.3.2 Depletion capacitance
2.3.3 Storage capacitance
2.3.4 Metal-substrate capacitance
2.4 Layout design rules
2.5 Analog and digital CMOS circuit design
2.5.1 Current mirrors
2.5.2 Inverter
2.5.3 NAND and NOR gates
2.5.4 Full adder
2.6 Conclusion
References
Chapter 3 Compact modeling of junctionless gate-all-around MOSFET for circuit simulation: Scope and challenges
3.1 Introduction
3.2 Specificities of compact models
3.3 Interest in hardware description language
3.4 Device’s operation and properties
3.5 Main approach and significant compact models
3.5.1 Charge-based model
3.5.2 Surface-potential-based model
3.5.3 Threshold-voltage-based model
3.6 Challenges with compact modeling
3.7 Conclusion
References
Chapter 4 Novel gate-overlap tunnel FETs for superior analog, digital, and ternary logic circuit applications
4.1 Introduction
4.2 Gate-overlap tunnel FETs for digital applications
4.2.1 Proposed GOTFET structures
4.2.2 Characteristics of the proposed GOTFETs
4.2.3 Implementation of digital basic building blocks
4.3 Gate-overlap tunnel FETs for ternary applications
4.3.1 Proposed GOTFET structures
4.3.2 Characteristics of the proposed GOTFETs
4.3.3 Proposed dual-threshold GOTFETs in the same device
4.3.4 Implementation of NTI, PTI, and STI ternary logic cells
4.4 Double gate line-tunneling FETs (DGLTFET) for analog applications
4.4.1 Proposed DGLTFET structures
4.4.2 Characteristics of the proposed GOTFETs
4.4.3 Analog applications of the line-tunneling TFETs
4.4.4 Vertical LTFET devices for analog circuit applications
4.4.5 Analog circuit design using vertical LTFET devices
4.5 Summary
References
Chapter 5 Phase transition materials for low-power electronics
5.1 Introduction
5.2 Phase transition material perspective
5.2.1 Theories behind MIT in PTM
5.2.2 Controlling parameters for MIT in PTM
5.2.3 Special focus on VO2 as PTM
5.2.4 Working of PTM
5.3 Applications of PTM in low-power electronics
5.3.1 PTM as two- or three-terminal electronic devices
5.3.2 Steep switching
5.3.3 Digital logics/circuits
5.3.4 Memory devices
5.3.5 Non-boolean computing architectures
5.3.6 Other applications
5.4 Conclusion
5.5 Future outlook
References
Chapter 6 Impact of total ionizing dose effect on SOI-FinFET with spacer engineering
6.1 Introduction
6.2 Radiation-hardened device structure and simulation setup
6.3 Results and discussion
6.3.1 TID response
6.3.1.1 Impact of radiation of spacer
6.3.1.2 Radiation-induced interface trap charges
6.3.1.3 Shift in threshold voltage after irradiation
6.3.1.4 Radiation affected subthreshold swing
6.4 Conclusion
References
Chapter 7 Scope and challenges with nanosheet FET-based circuit design
7.1 Introduction
7.2 Comparison of NS-FET with other structures
7.3 Temperature assessment of NS-FET
7.4 Doping assessment of NS-FET
7.5 Dimension assessment of nanosheets
7.6 Assessment of using high-K dielectric as gate oxide
7.7 Digital applications
7.8 Conclusion
References
Chapter 8 Scope with TFET-based circuit and system design
8.1 Introduction
8.2 Tunneling field-effect transistor
8.3 Scope and applications
8.3.1 TFET-based biosensors
8.3.2 TFET-based static random-access memories
8.4 Conclusion
References
Chapter 9 An overview of FinFET-based capacitorless 1T-DRAM
9.1 Introduction
9.1.1 Capacitorless 1T-DRAM
9.1.2 Operation of capacitorless 1T-DRAM
9.1.3 Scaling challenges
9.1.4 Finfet-based capacitorless 1T-DRAM
9.2 Device description
9.3 Simulation setup and model description
9.4 Result and discussion
9.5 Conclusion
References
Chapter 10 Literature review of the SRAM circuit design challenges
10.1 Introduction
10.2 Basic concepts and related terminologies
10.2.1 Fin field-effect transistor technology
10.2.2 SRAM memory architecture
10.3 FinFET-based SRAM cells
10.3.1 FinFET-6T SRAM cell structure
10.3.2 FinFET-7T SRAM cell structure
10.3.3 FinFET-8T SRAM cell structure
10.3.4 FinFET-9T SRAM cell structure
10.3.5 FinFET-10T SRAM cell structure
10.3.6 FinFET-11T SRAM cell structure
10.3.7 FinFET-12T SRAM cell structure
10.3.8 FinFET-13T SRAM cell structure
10.4 Performance assessment metrics
10.4.1 Static noise margin (SNM)
10.4.2 Temperature
10.4.3 Power and delay
10.4.4 Power delay product (PDP)
10.4.5 Read noise margin (RNM)
10.4.6 Write noise margin (WNM)
10.5 Analytical results of FinFET SRAM in different technologies
10.6 Analytical results of FinFET SRAM in different technologies
10.7 Conclusion
References
Chapter 11 Challenges and future scope of gate-all-around (GAA) transistors: Physical insights of device-circuit interactions
11.1 Introduction
11.2 The transition from planer FETs to 3D FETs
11.2.1 Benefits of SOI over bulk MOS
11.2.2 Benefits of dual gate over SOI
11.2.3 The emergence of 3D technology
11.3 Gate-all-around transistor family
11.3.1 The nanowire FET
11.3.2 The nanosheet transistor (NSFET)
Negative points to the NSFET
11.3.3 Junctionless NSFET
11.3.4 Tunnel junction NSFET
11.3.5 Forksheet FET
11.3.6 Complementary FET (CFET)
11.4 Challenges and future scope with the GAAFET family
11.5 Device-circuit interaction
11.5.1 Digital design perspectives
11.5.2 Analog design perspectives
11.6 Circuit-related reliability issues
11.6.1 Time-dependent dielectric breakdown (TDDB)
11.6.2 Hot carrier injection (HCI)
11.6.3 Bias temperature instability (BTI)
11.6.4 Design techniques for reliability
11.7 Conclusion
References
Index
