Nowadays over 50% of the integrated circuits are manufactured at wafer foundries. This book presents a foundry-integrated perspective of the field and is a comprehensive and up-to-date manual designed to serve process, device, layout, and design engineers. It includes chapters carefully selected to cover topics relevant for them to deal with their work. The book provides insight into the different types of design rules (DRs) and considerations for setting new DRs. It includes isolation, gate patterning, S/D, contacts, metal lines, MOL, air gaps, and so on. It explains in detail the layout rules needed to support advanced planarization processes, different types of dummies, and related utilities as well as presents a large set of guidelines and layout-aware modeling for RF CMOS and analog modules. It discusses the layout DRs for different mobility enhancement techniques and their related modeling, listing many of the dedicated rules for static random-access memory (SRAM), embedded polyfuse (ePF), and LogicNVM. Alongside the cookbook description, it provides the setting and calibration of the process parameters set and describes the 28 20 nm planar MOSFET process flow for low-power and high-performance mobile applications in a step-by-step manner. It also includes FEOL and BEOL physical and environmental test for qualifications together with automotive qualification and design for automotive (DfA). Written for the professionals, the book belongs to the bookshelf of microelectronic discipline experts.
Author(s): Eitan N. Shauly
Publisher: Jenny Stanford Publishing
Year: 2022
Language: English
Pages: 829
City: Singapore
Cover
Half Title
Title Page
Copyright Page
Table of Contents
Preface
Acknowledgment
Contributors
Chapter 1: Layout Design Rules: Definition, Setting, and Scaling
1.1: Introduction: The Goal of Design Rules
1.2: Different Types of Layout DRs
1.2.1: The WIDTH rule
1.2.2: The SPACE rule
1.2.3: The DISTANCE rule
1.2.4: The ENCLOSURE rule
1.2.5: The EXTENSION rule
1.2.6: The OVERLAP rule
1.2.7: The COVERAGE rule
1.2.8: The AREA1 rule
1.2.9: The AREA2 rule
1.2.10: The PERIPHERY rule
1.2.11: The PARALLEL LENGTH rule
1.2.12: The INTERACT rule
1.2.13: The NOT allowed rule
1.2.14: More Definitions and Examples for More Complex Rules
1.3: Different Considerations for Setting a New DR
1.4: Reliability Consideration for DR Setting
1.5: Device Sensitivity to Layout Proximity
1.6: Design Ranking
1.7: Standard Cells Digital Density and Layout Considerations
1.8: Device Considerations for Standard Cells
1.9: Restricted Design Rules
1.10: Gridded Design Rules
1.10.1: GDR (Regular-Fabric-Based) Design Methodology
1.11: Double Patterning
1.11.1: Resolution enhancement: the drive force for DP
1.11.2: Mask decomposition and colors conflicts: LELE integration
1.11.3: Mask decomposition (with line-cut) for SADP integration
1.11.4: Interconnect variation modeling under DP misalignment
1.11.5: DRC, anchoring, and standard cells placement
1.11.6: Dummy fill insertion under DP constrains
Chapter 2: Front-End-of-Line Topological Design Rules
2.1: Introduction
2.1.1: Minimum area rules (.A.1 and .A.2)
2.1.2: AA for oxide diffusion (OD) rules
2.1.2.1: AA width (AA.W.1)
2.1.2.2: Intra-well isolation (AA.S.1)
2.1.2.3: Enclosed AA (AA.A.2): STI stress-induced defectivity
2.1.2.4: The dependency of gate width and gate LER on AA width
2.1.3: WN (N-well) rules
2.1.3.1: N-well junction breakdown
2.1.3.2: N-well width (WN.W.1) and space (WN.S.1/2)
2.1.3.3: N-well as a protected diode (WN.A.1) and floating N-well (WN.N.1)
2.1.3.4: Inter-well isolation (AA.E.3, AA.D.3)
2.1.3.5: Layout considerations for well masks
2.1.3.6: Well (mask) proximity effect (WPE)
2.1.4: Guard rings and DNW rules
2.1.4.1: Integration of DNW
2.1.4.2: Isolation enhancement by native layer around the N-well ring
2.1.5: Threshold voltage complimentary (VTC) implant rules
2.1.5.1: Layout variability for VTC masks
2.1.6: DGO area rules
2.1.6.1: V MOSFETs threshold voltage shift
2.1.7: Poly GC rules
2.1.7.1: Core poly width (GC.W.1)
2.1.7.2: Core poly space (GC.S.1), space over STI (GC.S.2) and poly pitch
2.1.7.3: Width of poly for routing (over STI, GC.W.2)
2.1.7.4: GC.D.1: distance of poly over STI to related AA
2.1.7.5: Poly LER and layout sensitivity
2.1.7.6: GC.X.2: Extension of poly beyond AA (endcap)
2.1.8: 2nd poly mask for poly cut (P2MC) rules
2.1.8.1: Poly cut mask with SADP
2.1.9: N+ S/D and P+ S/D (NPSD) rules
Chapter 3: Back-End-of-Line Topological Design Rules
3.1: Introduction
3.1.1: Methodology for BEOL Design Rule Setting
3.1.2: Contact Related Rules
3.1.2.1: Contact width and space rules
3.1.2.2: Enclosure and extension of active and poly around contact
3.1.2.3: Distance of S/D contact to related gate
3.1.2.4: Non-square contacts
3.1.2.5: Optical-Proximity-Correction for contacts
3.1.2.6: DRs for contact formed by double patterning
3.1.3: Metal related rules
3.1.3.1: Metal width and space rules
3.1.3.2: Metal enclosed rules
3.1.4: Via Rules
3.1.4.1: Via width and space rules
3.1.4.2: Double-via and VIABAR rules
3.1.5: BEOL Reliability-Related Design Rules
3.1.5.1: Maximum current density in metal wires and contact/vias under DC conditions
3.1.5.2: Setting up design guidelines for metal width on the basis of EM failures
3.1.5.3: Via rules as extracted from stress-induced-voids measurements
3.1.5.4: Minimum metal space rules as extracted by TDDB measurements
3.1.6: Integration for Sub-28 nm Technology: Middle-of-Line
3.1.6.1: Local interconnects and middle-of-line (MOL) integration
3.1.6.2: Reliability of middle-of-line interconnects
3.1.6.3: Air gaps for capacitance reduction
Chapter 4: Coverage Rules and Insertion Utilities
4.1: Introduction: The Need for Planarization
4.2: CMP Planarization for Oxide and Cu
4.3: CMP Process Integration
4.3.1: Dishing and erosion
4.3.2: STI CMP process and the main challenges
4.3.3: Cu CMP process
4.3.4: Cu CMP modeling
4.3.5: Cu Electroplating
4.4: Global and Local Planarization
4.4.1: CMP Range (Density Interaction Distance)
4.5: AA, Poly, and Al Global Coverage Rules
4.6: AA and Copper Local Coverage Rules
4.7: Minimum and Maximum Copper Coverage Design Rule Setting
4.8: Dummy AA, Dummy Poly, and Dummy Metal Rules
4.8.1: Multilevel Coverage Integration Effects
4.8.2: Design-for-Manufacturing for Copper Lines
4.9: Different Methods for Dummy Fill Insertion
4.9.2: Single-Size Tile Filling
4.9.3: Rule-Based (Linear-Programing) Dummy Fill
4.9.4: Model-Based Driven Dummy Fill
4.9.5: Net-Aware and Timing-Aware DM Fill
4.9.6: More Advanced Fill Methods: Cell Fill
4.10: Capacitive Coupling of Dummies
4.11: The Effect of Dummy Fill on Wire Resistance and Inductance
4.12: The Effect of Dummy Fill on Inductors
4.13: Dummy Fill Blocking Layers
4.14: RTA-Aware Dummy Fill Insertion
4.15: Dummy Fill Considerations for Design Fix (ECO Fill)
4.16: Metal Slits Rules
4.16.1: Metal Slits Insertion Method and Utilities
4.17: Additional Coverage Rules (Not for AA, GC, Metals)
Chapter 5: Design Rules, Guidelines, and Modeling for Analog Modules
5.1: Introduction
5.2: Active Devices
5.2.1: MOSFETs
5.2.2: High-Voltage MOSFETs
5.2.3: Parasitic BJTs
5.3: Passive Devices
5.3.1: Analog DRs for FEOL Resistors
5.3.2: Analog DRs for FEOL Capacitors (MOSCAP, MOSVAR)
5.3.3: Analog DRs for BEOL Capacitors (MIM, MFC)
Chapter 6: Stress-Related Layout Design Rules and Modeling
6.1: Introduction
6.2: Mobility Dependent on Crystal Orientation (Notch Orientation)
6.3: Mobility Dependent on Surface Orientation (Hybrid Substrate)
6.4: Length of Diffusion and Oxide Space Effect Rules and Modeling
6.5: Stress from Silicided S/D Area
6.6: Poly Stress-Memorization Technique Layout Rules and Modeling
6.7: Source-Drain Stress-Memorization Technique
6.8: Contact Etch Stop Layer (cESL) Layout Rules and Modeling
6.9: Epitaxial (Embedded) SiGe (eSiGe) Layout Rules and Modeling
6.10: Compressive SiGe (cSiGe Layer) Layout Rules and Modeling
6.11: Modeling for cESL and eSiGe Stressors (Stress from S/D Area)
6.12: Advanced Technology Nodes with Integration of Several Stressors
Chapter 7: Dedicated Design Rules for Memory Modules
7.1: Introduction
7.2: Fuse and Antifuse Logic OTP Memories
7.2.1: Electrically (Programed) Poly Fuse (ePF)
7.2.2: MOSFET-Based Antifuse
7.3: Single-Poly FG Memories
7.3.1: Y-flash memory
7.3.2: Critical DRs Impact on Y-Flash Cell Operation
7.3.2.1: Special DRs of Y-flash cell
7.3.2.2: Coupling ratio of Y-flash cell
7.3.2.3: Programming/erasing performance of Y-flash cell
7.3.2.4: Endurance/retention
7.3.2.5: Array arrangement of Y-flash cells
7.4: Dedicated DRs for Single-Point SRAM
7.4.1: Dedicated DRs for “Tall” SRAM Type-D
7.4.2: Dedicated DRs for Wide SRAM
7.4.3: SRAM for High-Temperature Applications
Chapter 8: Planar CMOS Process Flow for Digital, Mixed-Signal, and RFCMOS Applications
8.1: Introduction: CMOS History in Short
8.2: Introduction: Power Dissipation and Leakage Components in Planar Technologies
8.3: 28 nm and 20 nm Planar Technology Description
8.4: Starting Material (Bulk Silicon, EPI Silicon)
8.4.1: Silicon Wafer: Module and Unit Steps Description
8.4.2: Typical Wafer Specification
8.5: Active Area for Oxide Definition Module
8.5.1: Active area (AA): module and unit steps description
8.5.2: Bulk defectivity and stress reduction in STI
8.6: Well Implant and Vt Control Module
8.6.1: Well and Vt implant: module and unit steps description
8.6.2: Super steep retrograde well implants
8.7: Gate Module (for High-k First, Gate Last)
8.7.1: Core gate oxide for 28 nm LP technology (poly/SiON)
8.7.2: Nitrogen doping by implant and Triple-Gate oxide (for 28 nm LP)
8.8: Gate Double Patterning (DP)
8.8.1: Double patterning with LELE
8.8.2: Double patterning with poly cut
8.8.3: The dependency of Poly CDs on Isolated/Dense, doped/un-doped poly
8.9: Offset Spacer and Extensions Implant Module
8.9.1: Junction leakage due to too shallow SDE and SD junction depth
8.9.2: Offset spacer
8.9.3: Extension implants (LDD, LATID, PAI)
8.9.4: Co-implants to minimize transient-enhanced diffusion (TED)
8.9.5: Cluster implants
8.9.6: Cryo-implants for advanced junction formation
8.9.7: Extension anneal
8.10: eSiGe PMOS Stressor and Spacer Definition Module
8.10.1: eSiGe stressor module
8.10.2: Spacer deposition and etchback
8.11: NSD and PSD Implant Module
8.11.1: Source-drain implant module
8.11.2: Source-drain anneal
8.12: Local Salicidation Module
8.13: Contact Etch Stop Layer (cESL) and Poly Open Polish (POP) Module
8.13.1: Contact etch stop layer
8.13.2: Poly open polish
8.14: N and P Work Function Module
8.14.1: Metal gate layer
8.14.2: PWF/NWF boundary effect
8.15: Contact Module
8.15.1: Cobalt metal for contacts
8.16: M1 Module
8.16.1: M1 low-k ILD deposition
8.16.2: M1 lithography and etch
8.16.3: Barrier metals and copper electroplating
8.16.4: Cu alloy and Cu capping (CoWP metal cap)
8.16.5: M1 etch stop layer
8.17: VI/MI Module
8.17.1: Via performance: resistance and reliability
8.17.2: Cu CMP and post-CMP clean
8.18: VL/ML Module
8.19: Passivation and Al for RDL Module
8.19.1: Wafer bonding
8.19.2: Electrical testing and final inspection
8.20: Flow Analysis
Chapter 9: Reliability Driven Design Rules
9.1: Introduction
9.2: Classification of Failure Modes
9.2.1: Early failure, random failure, and wear-out failure
9.2.2: Intrinsic and extrinsic mechanisms
9.2.3: Fatal failure and degradation failure modes
9.3: Foundry Physical Reliability Level-1
9.3.1: Qualification plan: JEP001
9.3.2: Front-End-of-Line physical qualification
9.3.3: Back-End-of-Line physical qualification
9.3.4: Metal-insulator-metal physical qualification
9.4: FEOL Reliability
9.4.1: Gate dielectrics
9.4.2: SILC, soft breakdown, and hard breakdown
9.4.3: Time-dependent dielectric breakdown
9.4.3.1: TDDB model
9.4.3.2: Statistics model
9.4.3.3: Appropriate detection of the first breakdown
9.4.3.4: Impact of carrier charging under electrical stress on lifetime prediction
9.4.4: Ramped voltage test (V-ramp)
9.4.4.1: Measurement of the ramped voltage test
9.4.4.2: Extraction of defect density
9.4.4.3: Issue in the ramped voltage test
9.4.5: Negative and positive bias temperature instability (NBTI/PBTI)
9.4.5.1: NBTI model
9.4.5.2: Charging component in NBTI and PBTI model
9.4.6: Hot carrier injection
9.5: Level 2 TDDB for MIM
9.5.1: TDDB for MIM
9.6: Plasma-Induced-Damage and Additional Qualification Tests
9.6.1: Plasma-induced damage process characterization
9.6.1.1: General background
9.6.1.2: PID physical qualification
9.6.1.3: Antenna ratio and PID rule definition
9.6.1.4: PID diode protection
9.6.1.5: PID on MIM capacitors
9.7: Additional Foundry Activities for Qualification
9.7.1: Electrical characterization and DRV
9.7.2: Formal platform construction analysis report
9.7.3: Reliability for RF applications
9.7.3.1: RF HCI testing
9.7.3.2: RF TDDB testing
9.7.3.3: RF NBTI testing
9.8: Automotive Qualification
9.8.1: Quality for automotive
9.8.2: Reliability for automotive
9.8.2.1: The mission’s profile
9.8.3: Automotive qualification plan
9.8.4: Design for automotive
9.8.4.1: Foundry PDK and infrastructure
9.8.4.2: Examples for dedicated automotive design rules
9.8.5: Functional safety methodologies for automotive
9.9: Foundry Environmental Reliability Level-2
9.9.1: Early life failure rate (ELFR) calculation
9.9.2: Early failure rate calculations
Index
