Continuous-Time Sigma-Delta A D Conversion: Fundamentals, Performance Limits and Robust Implementations (Advanced Microelectronics, Volume 21)

Contents......Page 9
1.1 Motivation and History......Page 22
1.3 Further Recommended Literature......Page 24
1.4 Organization of this Book......Page 26
2.1.1 Sampling and Quantization......Page 27
2.1.2 Quantizer White Noise Model......Page 30
2.2 Performance Metrics......Page 31
2.2.1 Frequency Domain Metrics......Page 32
2.2.2 Noise and Power Metrics......Page 33
2.2.3 Used Tools and Program Code......Page 35
2.3 Performance of Nyquist Rate Converters......Page 36
2.4 Performance of Oversampled Converters......Page 37
2.5 Oversampled Noise-Shaping Converters: ΣΔ ADC......Page 38
2.5.1 The First-Order ΣΔ Modulator......Page 40
2.5.2 Pattern-Noise and Dithering in ΣΔ Modulators......Page 41
2.6 Performance Increase in ΣΔ Modulators......Page 42
2.6.2 Higher Order ΣΔ Modulators......Page 43
2.6.3 Multibit ΣΔ Modulators......Page 44
2.7.1 Distributed Feedback Topology......Page 45
2.7.2 Feed-Forward Topology......Page 47
2.7.3 Local Feedback Loops......Page 48
2.7.4 ΣΔ Modulator Loop Filter Stability and Scaling......Page 49
2.7.5 Effective Quantizer Gain in ΣΔ Modulators......Page 52
2.8 Multiloop, Cascaded ΣΔ Modulators......Page 53
2.9 Specialized Architectures......Page 56
2.10 Loop Filters with Bandpass Characteristic......Page 57
3.1 CT ΣΔ Modulator Issues......Page 58
3.1.1 Sampling Operation......Page 59
3.1.2 Filter Realization......Page 60
3.1.3 Quantizer Realization......Page 61
3.1.4 Feedback Realization......Page 62
3.2 DT-to-CT Conversion of ΣΔ Modulators......Page 66
3.2.1 The Impulse-Invariant Transformation......Page 67
3.2.2 Modified Z-Transform......Page 71
3.2.3 Differences of the Two Transformations......Page 73
3.2.4 DT-to-CT Conversion of Cascaded ΣΔ Modulators......Page 74
3.3 Direct Filter Synthesis......Page 80
3.4 STF and NTF in CT ΣΔ Modulators......Page 82
3.5 Implicit Antialiasing Filter in CT ΣΔ Modulators......Page 84
3.5.1 Implicit AAF of the CT Third-Order Modulator......Page 85
3.5.2 Implicit AAF of the CT SOFO Modulator......Page 88
3.7.1 gmC-Integrator......Page 90
3.7.2 LC-Resonator......Page 92
3.7.3 Active gmC-Integrator......Page 93
3.7.5 Log-Domain Integrator......Page 94
3.7.6 Active RC-Integrator......Page 95
3.7.8 Conclusion on the Commonly Used CT Integrators......Page 96
3.8 Classification of Non-Idealities in CT ΣΔ Modulators......Page 97
3.8.1 Input Referred Errors/Different Locations of Error Occurrence or Input Referred Nonidealities......Page 100
3.8.2 Organization of the Following Chapters......Page 102
4.2 Excess Loop Delay in Continuous-Time ΣΔ Modulators......Page 104
4.2.1 Coefficient Mismatch through Excess Loop Delay......Page 105
4.2.2 Increased Modulator Order through Excess Loop Delay......Page 106
4.2.3 Alternative Approach to the Effect of Excess Loop Delay......Page 107
4.2.4 Compensation for Excess Loop Delay in CT ΣΔ Modulators......Page 108
4.2.5 Simulation Results on Excess Loop Delay......Page 111
4.3.1 Jitter Effects in CT ΣΔ Modulators......Page 113
4.3.2 Calculation of the Jitter Influence for Rectangular Feedback......Page 115
4.3.3 Reduction of Clock Jitter Influence Using Multibit DACs......Page 118
4.3.4 Reduction of Clock Jitter Influence Using Shaped Feedback Waveform DACs......Page 119
4.3.5 Further Possibilities for CT ΣΔ Modulators with Reduced Clock Jitter Sensitivity......Page 125
4.3.6 CT Loop Filters Employing Shaped Feedback Waveforms......Page 126
4.3.7 Trade-off for Reduced Clock Jitter Sensitivity......Page 127
4.3.8 Discussion on the White Clock Jitter Model......Page 128
4.3.9 Simulation Results on Clock Jitter......Page 129
4.4 DAC Slew Rate Limitation......Page 132
4.5 DAC Nonlinearity......Page 133
5.1.1 Analytical Description of the Nonideal CT Filter Behavior......Page 135
5.1.2 Quantitative Impact of Nonideal CT Filter Behavior......Page 136
5.2 Finite OpAmp Gain......Page 137
5.3 Integrator Gain or Time-Constant Error......Page 139
5.3.1 Effective Quantizer Gain and Integrator Gain Errors......Page 140
5.3.2 Single-Loop Modulators......Page 141
5.3.3 Cascaded Modulators......Page 142
5.3.4 Simulation Results......Page 143
5.3.6 Compensation of Gain Errors in Cascaded ΣΔ Modulators......Page 144
5.4 Finite Amplifier Gain-Bandwidth Product......Page 146
5.4.1 Basic Analytical Description of Finite GBW......Page 147
5.4.2 Extended Model for Single-Loop Modulators......Page 149
5.4.3 Compensation for Finite GBW-Induced Errors in CT ΣΔ Modulators......Page 152
5.4.4 Influence on Different Feedback Implementations......Page 157
5.5.1 Slew Rate in CT ΣΔ Modulators......Page 159
5.5.2 Influence of Different Feedback Waveforms and ΣΔ Architectures......Page 160
5.5.3 Simulation Results......Page 161
5.6.1 Limited Output Swing......Page 164
5.6.2 Circuit Noise......Page 165
5.6.3 Integrator Nonlinearity......Page 168
6 Quantizer Nonidealities in Continuous-Time ΣΔ Modulators......Page 172
7.1 FOM Based Design Strategy for CT ΣΔ Modulators......Page 174
7.1.1 Generic Figure of Merit Calculation......Page 175
7.1.2 Single-Loop Architectures......Page 177
7.1.3 Multibit Single-Loop Architectures......Page 178
7.1.4 Cascaded Architectures......Page 179
7.1.5 FOM Based Design Example: A 12-Bit 25 kHz ΣΔ Modulator......Page 180
7.1.6 Expansion Features of the FOM Based Design Strategy......Page 181
7.2.1 Low-Power Limits in Noise-Dominated Circuits......Page 182
7.2.3 Low-Power Limits in Matching-Dominated Circuits......Page 183
7.2.4 Low-Power Limits in ΣΔ Modulators......Page 184
7.3 Implementation Example I: A 12-Bit 25 kHz 1.5 V CT ΣΔ Modulator......Page 186
7.3.1 Loop Filter Design......Page 187
7.3.2 Circuit Blocks......Page 191
7.3.3 Modulator Design......Page 195
7.3.4 Measurements......Page 198
7.4.1 SCR-Feedback Implementation......Page 202
7.4.2 SCR Time Constant and Loop Filter Scaling......Page 203
7.4.3 Experimental Results......Page 205
7.4.4 CT ΣΔ Modulator with SCR-I-Feedback......Page 206
7.5.1 Modulator Architecture......Page 208
7.5.2 Loop Filter......Page 209
7.5.3 Circuit Implementation......Page 212
7.5.5 Experimental Results......Page 220
7.6 Implementation Example IV: A 2-1-1 Cascaded CT ΣΔ Modulator......Page 223
7.6.2 Measured Ideal Modulator Performance......Page 224
7.6.3 Verification of the Digital Gain-Error Cancellation......Page 226
A. Program Code......Page 229
B. General Loop Filter Pole Transformation for the Exponential Feedback......Page 231
C. On the CT Integrator, Sampling Frequency f[sub(S)] and the Amplifier GBW......Page 232
References......Page 235
G......Page 253
N......Page 254
S......Page 255
W......Page 256