Computer Organization and Design RISC-V Edition: The Hardware Software Interface

Front Cover
In Praise of Computer Organization and Design: The Hardware/Software Interface, Sixth Edition
Computer Organization and Design: THE HARDWARE SOFTWARE INTERFACE
Author bio
Computer Organization and Design: THE HARDWARE SOFTWARE INTERFACE
Copyright
Dedication
Contents
Preface
1 - Computer Abstractions and Technology
1.1 Introduction
1.2 Seven Great Ideas in Computer Architecture
1.3 Below Your Program
1.4 Under the Covers
1.5 Technologies for Building Processors and Memory
1.6 Performance
1.7 The Power Wall
1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors
1.9 Real Stuff: Benchmarking theIntel Core i7
1.10 Going Faster: Matrix Multiply in Python
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspective and Further Reading
1.14 Self-Study
1.15 Exercises
2 - Instructions: Language of the Computer
2.1 Introduction
2.2 Operations of the Computer Hardware
2.3 Operands of the Computer Hardware
2.4 Signed and Unsigned Numbers
2.5 Representing Instructions in the Computer
2.6 Logical Operations
2.7 Instructions for Making Decisions
2.8 Supporting Procedures in Computer Hardware
2.9 Communicating with People
2.10 RISC-V Addressing for Wide Immediates and Addresses
2.11 Parallelism and Instructions:Synchronization
2.12 Translating and Starting a Program
2.13 A C Sort Example to Put it All Together
2.14 Arrays versus Pointers
2.16 Real Stuff: MIPS Instructions
2.17 Real Stuff: ARMv7 (32-bit) Instructions
2.18 Real Stuff: ARMv8 (64-bit) Instructions
2.19 Real Stuff: x86 Instructions
2.20 Real Stuff: The Rest of the RISC-VInstruction Set
2.21 Going Faster: Matrix Multiply in C
2.22 Fallacies and Pitfalls
2.23 Concluding Remarks
2.25 Self-Study
2.26 Exercises
3 - Arithmetic for Computers
3.1 Introduction
3.2 Addition and Subtraction
3.3 Multiplication
3.4 Division
3.5 Floating Point
3.6 Parallelism and Computer Arithmetic:Subword Parallelism
3.7 Real Stuff: Streaming SIMD Extensionsand Advanced Vector Extensions in x86
3.8 Going Faster: Subword Parallelism and Matrix Multiply
3.9 Fallacies and Pitfalls
3.10 Concluding Remarks
3.11 Historical Perspective and Further Reading
3.12 Self-Study
3.13 Exercises
4 - The Processor
4.1 Introduction
4.2 Logic Design Conventions
4.3 Building a Datapath
4.4 A Simple Implementation Scheme
4.5 A Multicycle Implementation
4.6 An Overview of Pipelining
4.7 Pipelined Datapath and Control
4.8 Data Hazards: Forwarding versus Stalling
4.9 Control Hazards
4.10 Exceptions
4.11 Parallelism via Instru
4.12 Putting It All Together: The Intel Core i76700 and ARM Cortex-A53
4.13 Going Faster: Instruction-LevelParallelism and Matrix Multiply
4.14 Advanced Topic: An Introduction to DigitalDesign Using a Hardware Design Languageto Describe and Model a Pipeline andMore Pipelining Illustrations
4.15 Fallacies and Pitfalls
4.16 Concluding Remarks
4.17 Historical Perspective and Further Reading
4.18 Self-Study
4.19 Exercises
5 - Large and Fast: Exploiting Memory Hierarchy
5.1 - Introduction
5.2 Memory Technologies
5.3 The Basics of Caches
5.4 Measuring and Improving Cache Performance
5.5 Dependable Memory Hierarchy
5.6 Virtual Machines
5.7 Virtual Memory
5.8 A Common Framework for Memory Hierarchy
5.9 Using a Finite-State Machine to Control aSimple Cache
5.10 Parallelism and Memory Hierarchy:Cache Coherence
5.11 Parallelism and Memory Hierarchy:Redundant Arrays of Inexpensive Disks
5.12 Advanced Material: Implementing CacheControllers
5.13 Real Stuff: The ARM Cortex-A8 and IntelCore i7 Memory Hierarchies
5.14 Real Stuff: The Rest of the RISC-VSystem and Special Instructions
5.15 Going Faster: Cache Blocking and Matrix Multiply
5.16 Fallacies and Pitfalls
5.17 Concluding Remarks
5.18Historical Perspective and FurtherReading
5.19 Self-Study
5.20 Exercises
6 - Parallel Processors from Client to Cloud
6.1 Introduction
6.2 The Difficulty of Creating Parallel Processing Programs
6.3 SISD, MIMD, SIMD, SPMD, and Vector
6.4 Hardware Multithreading
6.5 Multicore and Other Shared Memory Multiprocessors
6.6 Introduction to Graphics Processing Units
6.7 Domain-Specific Architectures
6.8 Clusters, Warehouse Scale Computers,and Other Message-Passing Multiprocessors
6.9 Introduction to Multiprocessor NetworkTopologies
6.10 Communicating to the Outside World:Cluster Networking
6.11 Multiprocessor Benchmarks and Performance Models
6.12 Real Stuff: Benchmarking the GoogleTPUv3 Supercomputer and an NVIDIAVolta GPU Cluster
6.13 Going Faster: Multiple Processors andMatrix Multiply
6.14 Fallacies and Pitfalls
6.15 Concluding Remarks
6.16 Historical Perspective and Further Reading
6.17 Self-Study
6.18 Exercises
A - The Basics of Logic Design
A.1 Introduction
A.2 Gates, Truth Tables, and Logic Equations
A.3 Combinational Logic
A.4 Using a Hardware Description Language
A.5 Constructing a Basic ArithmeticLogic Unit
Index
0-9, and symbols
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
B - Graphics and Computing GPUs
B.1 Introduction
B.2 GPU System Architectures
B.3 Programming GPUs
B.4 Multithreaded MultiprocessorArchitecture
B.5 Parallel Memory System
B.6 Floating-point Arithmetic
B.7 Real Stuff: The NVIDIA GeForce 8800
B.8 Real Stuff: Mapping Applications to GPUs
B.9 Fallacies and Pitfalls
B.10 Concluding Remarks
B.11 Historical Perspective and Further Reading
C- Mapping Control to Hardware
C.1 Introduction
C.2 Implementing Combinational Control Units
C.3 Implementing Finite-State Machine Control
C.4 Implementing the Next-State Functionwith a Sequencer
C.5 Translating a Microprogram to Hardware
C.6 Concluding Remarks
C.7 Exercises
D - Survey of Instruction Set Architectures
D. 1 Introduction
D.2 A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
D.3 The Intel 80×86
D.4 The VAX Architecture
D.5 The IBM 360/370 Architecture forMainframe Computers
Answers to Check Yourself
D.6 Historical Perspective and References
Answers to Check Yourself
Glossary
Further Reading
IBC