This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.
Author(s): Pallavi Srivastava
Publisher: Springer
Year: 2022
Language: English
Pages: 128
City: Cham
Preface
Acknowledgements
Contents
Acronyms
1 Introduction to Asynchronous Circuit Design
1.1 Introduction
1.2 Evolution of Asynchronous Design Style
1.3 Why Asynchronous?
1.3.1 Synchronous vs Asynchronous: How to Choose?
1.4 Book Organisation
1.5 Chapter Summary
References
2 Preliminary Considerations for Asynchronous Circuit Design
2.1 Definitions
2.2 Delay Assumptions
2.2.1 Fundamental Mode or Huffman Circuit
2.2.2 Speed Independent or Muller Circuit
2.2.3 Delay-Insensitive Circuit
2.2.4 Quasi-Delay-Insensitive Circuit
2.2.5 Other Approaches
2.3 Communication Protocols
2.3.1 Data Encoding
2.3.2 Data Flow Direction
2.3.3 Signaling Protocols
2.4 Necessity of Completion Detection in Asynchronous Design
2.5 Chapter Summary
References
3 Completion Detection Schemes for Asynchronous Design Style
3.1 Introduction
3.2 M-of-N Encoding Protocol
3.2.1 Muller's C-Element
3.2.2 Dual-Rail Protocol
3.3 Bundled Data Protocol
3.3.1 Completion Detection in Bundled Data Circuits
3.4 Analysis of Completion Detection Schemes
3.4.1 Bundled Data vs Dual-Rail Protocol
3.5 Chapter Summary
References
4 Case Studies: Barrel Shifter and Binary Adders
4.1 Barrel Shifter
4.1.1 Architecture of a Conventional Barrel Shifter (CBS)
4.1.2 Asynchronous Bundled Data Barrel Shifter
4.2 Binary Adders
4.2.1 Asynchronous Bundled Data Adder
4.3 Chapter Summary
Appendix
4.4 Fundamentals of Binary Adders
4.4.1 Ripple Carry Adder (RCA)
4.4.2 Carry Look Ahead Adder (CLA)
4.4.3 Brent-Kung Adder
References
5 Generic Architecture of Deterministic Completion Detection Scheme
5.1 Design Methodology
5.1.1 Preliminary Stage
5.1.2 Design and Development Stage
5.1.3 Application Stage
5.2 Deterministic Completion Detection Scheme
5.2.1 Deterministic Completion Detection Circuit (DCDC)
5.2.2 Delay Generating Unit (DGU)
5.3 Chapter Summary
References
6 Architecture Optimisation Using Deterministic Completion Detection
6.1 Asynchronous Bundled Data Barrel Shifter
6.1.1 Single-Precision Conventional Barrel Shifter
6.2 Deterministic Completion Detection Scheme for Single-Precision ABBS
6.2.1 DCDC for ABBS
6.2.1.1 Output Selection Stage (OSS)
6.2.1.2 Shift Dependent Selector (SDS)
6.2.2 DGU for ABBS
6.2.3 Delay Calculation
6.3 Asynchronous Bundled Data Binary Adder
6.3.1 Single-Precision Binary Adder
6.4 Deterministic Completion Detection Scheme for Single-Precision ABBA
6.4.1 DCDC for ABBA
6.4.2 DGU for ABBA
6.5 Chapter Summary
References
7 Simulations
7.1 Evaluation of a Single-Precision Barrel Shifter
7.1.1 An Illustrative Example
7.2 Evaluation of a Single-Precision Binary Adder
7.2.1 Results of ABBA
7.3 Other Applications
7.4 Suggestions for Future Work
7.5 Chapter Summary
References
A Floating-Point Addition
References
B Shifter Test Bench
Index
