Complete PCB Design Using OrCad Capture and Layout

Complete PCB Design Using OrCad Capture and Layout......Page 2
Table of Contents......Page 4
Using OrCAD Capture and Layout......Page 16
Acknowledgments......Page 20
Computer-Aided Design and the OrCAD Design Suite......Page 22
PCB cores and layer stack-up......Page 23
Photolithography and chemical etching......Page 26
Mechanical milling......Page 29
Layer registration......Page 30
Function of OrCAD Layout in the PCB Design Process......Page 32
Postprocess (Gerber) fi les......Page 35
PCB assembly layers and fi les......Page 36
Creating a Circuit Design with Capture......Page 38
Starting a new project......Page 39
Placing parts......Page 42
Creating the Layout netlist in Capture......Page 44
Starting Layout and importing the netlist......Page 46
Making a board outline......Page 51
Placing the parts......Page 52
Manual routing......Page 53
Locking traces......Page 55
Postprocessing the board design for manufacturing......Page 56
Capture projects explained......Page 60
Capture part libraries explained......Page 63
The AutoECO utility......Page 65
The session frame and Design window......Page 67
The toolbar......Page 68
General project tool buttons......Page 69
Selection tools......Page 71
Environmental control tools......Page 74
Manual board route/Edit Mode tools......Page 75
Interactive manual routing tools......Page 76
Other indicators and controls......Page 77
Controlling the autorouter......Page 78
Locking traces......Page 80
Postprocessing and layer details......Page 82
Table 3-3 Gerber and documentation fi les generated during postprocessing (Continued)......Page 83
Understanding the documentation files......Page 84
Other tools used with Layout......Page 85
CHAPTER 4 Introduction to Industry Standards......Page 86
Electronic Industries Alliance (EIA)......Page 87
Institute of Electrical and Electronics Engineers (IEEE)......Page 88
Producibility levels......Page 89
OrCAD Layout design complexity levels—IPC performance classes......Page 90
Breakout and annular ring control......Page 91
Standard panel sizes......Page 92
Standard fi nished PCB thickness......Page 93
Prepreg thickness......Page 94
Copper thickness for PTHs and vias......Page 95
Copper Trace and Etching Tolerances......Page 96
Standard Hole Dimensions......Page 97
Other items of interest......Page 98
Assembly Processes......Page 100
Automated assembly processes (pick and place)......Page 101
Soldering Processes......Page 102
Wave soldering......Page 103
Refl ow soldering......Page 105
Component Placement and Orientation Guide......Page 106
Holes and jumper wires......Page 107
Table 5-1 Minimum recommended spacing for discrete, axial THDs......Page 108
Table 5-2 Minimum recommended spacing for discrete, radial THDs......Page 109
Table 5-3 Minimum recommended spacing for through-hole mounted ICs......Page 110
Table 5-4 Minimum recommended spacing between through-hole discretes and ICs......Page 111
Table 5-5 Minimum recommended spacing for holes and jumper wires......Page 112
Table 5-6 Minimum recommended spacing for discrete SMDs......Page 113
Table 5-7 Minimum recommended spacing for IC SMDs......Page 114
Land Patterns for Surface-Mounted Devices......Page 115
Figure 5-6 JEDEC package dimensions (typical convention).......Page 116
SMD padstack design......Page 117
Table 5-9 Nominal heel solder fi llet values (JH) by package type......Page 118
Figure 5-9 Padstack spreadsheet for design......Page 119
Figure 5-10 IPC-7351 land pattern description of an eight-pin SOIC......Page 120
Table 5-11 Courtyard excess (protrusion) by density level for various SMDs......Page 121
Land Patterns for Through-hole Devices......Page 122
Figure 5-12 Radial-leaded through-hole device. (a) Axial-leaded capacitor. (b) Layout axial footprint......Page 123
Hole-to-lead ratio......Page 124
Table 5-13 Hole-to-lead size relationship by producibility level......Page 125
Table 5-15 SFAs for PTH design......Page 126
Figure 5-15 PTH or via with oversized lands overlapping plane.......Page 127
Soldermask and solder paste dimensions......Page 128
Noise......Page 130
Distortion......Page 131
Electromagnetic Interference and Cross Talk......Page 132
Magnetic fi elds and inductive coupling......Page 133
Figure 6-3 Voltage induced into adjacent trace by varying magnetic fi elds.......Page 135
Figure 6-4 Loop inductance of a closed circuit.......Page 136
Figure 6-6 Aiding and opposing magnetic fi elds. (a) Aiding fi elds. (b) Opposing fi elds.......Page 137
Electric fi elds and capacitive coupling......Page 138
Table 6-1 IEEE/ANSI Standard Ground Symbols......Page 140
(b) Series connected.......Page 141
Figure 6-10 The actual circuit—the hidden schematic.......Page 142
Ground (return) planes......Page 143
Figure 6-13 A CMOS logic gate.......Page 144
Figure 6-14 Illustration of ground bounce and rail collapse.......Page 145
Split power and ground planes......Page 146
(c) Moated plane. (d) Isolated, continuous planes.......Page 147
Characteristic impedance......Page 148
Figure 6-19 A signal applied to the transmission line.......Page 149
Figure 6-20 The instantaneous impedance propagates along the transmission line.......Page 150
Figure 6-21 Wave velocity vs particle velocity.......Page 151
Table 6-3 Embedded microstrip transmission lines......Page 153
Table 6-5 Unbalanced stripline......Page 154
Figure 6-22 Positively refl ected wave (ZT is an open circuit).......Page 155
Figure 6-23 Negatively refl ected wave (ZT is a short circuit).......Page 157
Figure 6-24 No refl ection (ZT absorbs wave energy).......Page 158
Figure 6-25 Representation of signal propagation on a PCB trace.......Page 159
Electrically long traces......Page 160
Figure 6-26 Ringing on an electrically long transmission line.......Page 161
Figure 6-27 Representation of an electrically short trace.......Page 162
Critical length......Page 163
Transmission line terminations......Page 164
Figure 6-30 No refl ections when all impedances are matched.......Page 165
Parts placement for electrical considerations......Page 166
Figure 6-32 Board layout recommendations for noisy circuits.......Page 167
PCB layer stack-up......Page 168
Figure 6-34 Six-layer stack-up examples.......Page 170
Figure 6-36 A 10-layer PCB stack-up.......Page 171
Trace width for current carrying capability......Page 172
Figure 6-38 Minimum trace widths for 1 oz copper for ∆T  10C.......Page 173
Trace width for controlled impedance......Page 174
Table 6-6a Microstrip transmission line confi gurations......Page 176
Table 6-6b Microstrip transmission line confi gurations......Page 177
Table 6-7a Stripline transmission line confi gurations......Page 180
Table 6-7b Stripline transmission line confi gurations......Page 181
Table 6-8 Minimum Conductor Spacing (Mils)......Page 184
(b) 3w spacing to minimize cross talk.......Page 185
Figure 6-42 Trace geometry of a sharp 90 corner.......Page 186
p. 174; Montrose 1999, p. 220; Bogatin, p. 315)......Page 187
The Capture Part Libraries......Page 188
Figure 7-1 Homogeneous—one or more identical parts in a package.......Page 189
Pins......Page 190
The pin tools......Page 191
The zoom tools......Page 192
Method 1: Constructing Parts Using the New Part Option......Page 193
Design example for a passive, homogeneous part......Page 194
Figure 7-6 New Part Properties dialog box.......Page 195
Figure 7-8 Grid settings in Options → Preferences dialog box.......Page 196
Figure 7-9 The Place Pin dialog box.......Page 197
Figure 7-11 Making coils with the Place Arc tool.......Page 198
Figure 7-13 Completed part with pin names and numbers visible.......Page 199
(a) User Properties dialog box (Part Properties). (b) Edit Properties dialog box......Page 200
Figure 7-17 New Part Properties dialog box for a dual op-amp.......Page 201
Figure 7-18 Dual op-amp, part A.......Page 202
Figure 7-20 Package view of dual op-amp part.......Page 203
Assigning power pin visibility......Page 204
Figure 7-23 A heterogeneous, multipart relay. (a) Relay package. (b) Relay schematic.......Page 205
Figure 7-25 Relay coil and diode.......Page 206
Figure 7-26 (a) Schematic and (b) pin settings for the fi rst set of relay contacts.......Page 207
Design Spreadsheet......Page 208
Figure 7-30 The New Part Creation Spreadsheet.......Page 209
Figure 7-32 Package view of new parts generated using the spreadsheet.......Page 210
Tools Menu......Page 211
Figure 7-34 Structure of Library Manager after copying a library into an existing library.......Page 212
Method 4: Generating Parts with the PSpice Model Editor......Page 213
Generating a Capture part library from a PSpice model library......Page 214
New Capture Parts......Page 215
Figure 7-39 New RS2A PSpice model in the Model Editor.......Page 216
Making a PSpice model from a Capture project......Page 217
Adding PSpice templates (models) to preexisting Capture parts......Page 227
Figure 7-51 Create Netlist dialog box.......Page 226
Figure 7-49 Place Hierarchical Port dialog box.......Page 225
Figure 7-48 PSpice probe window for the center-tap transformer.......Page 224
Figure 7-47 Simulation Settings dialog box.......Page 223
Figure 7-46 Part Property Editor spreadsheet (vertical view).......Page 222
Figure 7-44 Place Ground dialog box.......Page 221
Figure 7-43 Place Part dialog box.......Page 220
Figure 7-41 The Create PSpice Project dialog box.......Page 219
Figure 7-40 New Project dialog box for a PSpice project.......Page 218
Constructing Capture Symbols......Page 229
Introduction to the Library Manager......Page 232
Conventions......Page 233
Layout’s footprint libraries......Page 234
Table 8-1 Foot print library categories (full version onl......Page 235
Figure 8-3 A 24-pin dual inline package (DIP-24) and its dimensions.......Page 236
(b) OEM-suggested land pattern.......Page 237
Padstacks......Page 238
Obstacles......Page 239
selection list.......Page 240
(c) Insertion origin.......Page 241
The Basic Footprint Design Process......Page 242
Figure 8-10 Starting a new footprint from the Library Manager.......Page 243
Figure 8-13 The Edit Obstacle dialog box.......Page 244
Silkscreen and Place Outline obstacles, and text.......Page 245
Figure 8-15 The Save Footprint As... dialog box.......Page 246
Working with Padstacks......Page 247
Accessing existing padstacks......Page 248
Editing padstack properties from the spreadsheet......Page 249
Saving footprints and padstacks......Page 250
Figure 8-20 Edit Padstack dialog boxes. (a) Global layer editing. (b) Single layer editing.......Page 251
Figure 8-21 Footprint design fl ow.......Page 252
(b) Land pattern (units in mm).......Page 253
Figure 8-23 System Settings dialog box (from Options menu).......Page 254
Figure 8-24 Padstacks spreadsheet and Edit dialog box.......Page 255
Figure 8-25 Assigning the new padstack.......Page 256
Figure 8-26 SOT-523 footprint with silk screen and place outline obstacles.......Page 257
Figure 8-27 Completed SOT-523 footprint.......Page 258
Figure 8-28 Footprint requirements for an axially leaded resistor.......Page 259
Figure 8-29 Completed 78R38 padstack.......Page 262
Figure 8-30 Grab locations for resizing obstacles.......Page 263
Introduction......Page 264
(b) Padstack parameters.......Page 265
Figure 8-35 PGA padstack properties.......Page 266
Figure 8-37 Pad Array Generator dialog box.......Page 267
Figure 8-39 Pad array design aids. (a) Array preview. (b) Array style sample.......Page 268
Footprint design for BGAs......Page 269
Figure 8-42 A 15
15 BGA as seen from the bottom.......Page 270
Figure 8-43 A 10
10 BGA footprint from the BGA library (viewed from top).......Page 271
Figure 8-45 Details of a “dogbone” fanout for a BGA.......Page 272
defi ned—preferred.......Page 273
Figure 8-47 Dimensions for fi ctitious 16-pin BGA (units in mils).......Page 274
Figure 8-48 BGA fan-out via defi nitions.......Page 275
Figure 8-49 Pad array generator setup for 4
4 practice BGA.......Page 276
Figure 8-50 Initial view of the 16-pin practice BGA.......Page 277
Figure 8-52 The completed pre-fanned out BGA.......Page 278
Figure 8-53 Various via technologies and their applications.......Page 279
Table 8-2 Basic hole types......Page 280
Table 8-3 Padstack defi nitions for various hole types......Page 281
Printing a catalog of a footprint library......Page 282
CHAPTER 9 PCB Design Examples......Page 284
Overview of the Design Flow......Page 285
Example 1: Dual Power Supply, Analog Design......Page 287
Figure 9-2 Analog circuit for design Example 1.......Page 288
Figure 9-3 Setting up a new project with the Project Wizard.......Page 289
Placing parts......Page 290
Table 9-2 Capture library parts list......Page 291
Figure 9-6 Choosing parts from the Place Part dialog box.......Page 292
Making power and ground connections......Page 293
Figure 9-7 Placing global power symbols.......Page 294
Figure 9-8 Determining a power pin’s type and name.......Page 295
Figure 9-10 Use the Display Properties dialog box to change a power symbol’s name.......Page 296
Figure 9-11 Part properties spreadsheet.......Page 297
Figure 9-12 Generating a bill of materials to include PCB footprints.......Page 298
Figure 9-13 Find and copy the name of the footprint in Layout.......Page 299
Figure 9-14 Assigning footprints to multiple parts with the Property Editor.......Page 300
Grouping related components......Page 301
Figure 9-17 Using the Property Editor to assign components to groups.......Page 302
Annotation......Page 303
Figure 9-20 Performing a design annotation.......Page 304
Figure 9-21 The Capture Design Rules Check dialog box.......Page 305
Figure 9-22 Creating a circuit netlist for Layout from Capture.......Page 306
Determining trace width......Page 307
Table 9-5 Analog design constraints and applicable technology fi les......Page 308
Importing the design into Layout......Page 309
Figure 9-24 Using the AutoECO to begin a new PCB design in layout.......Page 310
Figure 9-26 Adding a footprint library to the AutoECO tool’s library list.......Page 311
Figure 9-27 Initial view of the analog design.......Page 312
Figure 9-28 Using Edit Component dialog box to add mounting holes.......Page 313
Adding dimension measurements......Page 314
Figure 9-30 Use the Edit Padstack dialog box to make a padstack nonplated.......Page 315
Figure 9-32 Relative and absolute dimension lines.......Page 316
Placing parts......Page 317
Finding parts......Page 318
Placing parts in the queue......Page 319
Intertool communication......Page 322
Setting up the layers......Page 323
Figure 9-40 Converting a routing layer to a plane layer.......Page 324
Assigning nets to layers......Page 325
Figure 9-42 Assigning power/ground nets to plane layers.......Page 326
Figure 9-43 Assigning alternate vias to a net.......Page 327
Figure 9-44 Route Settings dialog box to specify via usage.......Page 328
Figure 9-45 Specifying fanout settings.......Page 329
Figure 9-46 Through-hole pins connected to planes by thermal reliefs.......Page 330
Figure 9-47 Fanned out power and ground nets in different colors.......Page 331
(b) “Pin to plane” method.......Page 332
Using free vias......Page 333
Figure 9-50 A completed pin-to-plane fanout method.......Page 334
Figure 9-51 Viewing Error Markers.......Page 335
Figure 9-52 Errors caused by padstack settings on a defi ned plane layer.......Page 336
Autorouting the board......Page 337
Controlling the route box......Page 338
Checking routing statistics......Page 339
Figure 9-54 Board after autorouting.......Page 340
Figure 9-56 Clearing Route Pass fl ags to redo autoroute.......Page 341
Figure 9-57 Setting up back annotation settings in Capture.......Page 342
Mixed-signal circuit design in Capture......Page 343
Table 9-6 Design parts list and schematic and footprint libraries......Page 344
Power and ground connections to digital and analog parts......Page 345
Figure 9-60 Connection of the analog and digital grounds.......Page 346
Figure 9-62 Select ground net name (analog or digital).......Page 347
Using busses for digital nets......Page 348
Figure 9-63 A mixed-signal power and ground system.......Page 349
Table 9-7 Mixed-signal PCB design constraints and applicable technology fi les......Page 350
Establishing a primary power plane......Page 351
(b) VCC net assignment (primary).......Page 352
Figure 9-68 Global power and ground nets.......Page 353
Figure 9-69 Controlling thermal relief and fanout settings.......Page 354
Creating split ground planes......Page 355
Figure 9-71 Setting up a free track (anti-copper) to split the ground plane.......Page 356
Creating nested power planes with copper pours......Page 357
Figure 9-73 Using a copper pour as a secondary net on a plane layer.......Page 358
Figure 9-74 Copper pours added to the power plane.......Page 359
Figure 9-75 Use a copper area obstacle to remove copper from a plane layer.......Page 360
(b) Second copper area.......Page 361
Figure 9-77 The routed board generated by the Layout autorouter.......Page 362
Moving a routed trace to a different layer......Page 363
Figure 9-78 The mixed-signal board after routing and cleanup.......Page 364
Figure 9-79 Using a copper pour to place a ground plane on a routing layer.......Page 365
Figure 9-81 Using a copper area and free vias to add ground areas.......Page 366
Figure 9-82 Setup for small free via.......Page 367
Setting the copper pour spacing......Page 368
Figure 9-84 Copper pour after changing clearances.......Page 369
Routing guard traces and rings......Page 370
Figure 9-86 Edit Obstacle dialog box for defi ning an anti-copper area.......Page 371
Figure 9-88 Examples of guard traces and guard rings.......Page 372
Figure 9-89 Multiple ground planes for one ground net, multiple connections.......Page 373
Figure 9-90 A multipower/multiground system with a chassis shield.......Page 374
Figure 9-91 A shorting strip used as a plane-to-plane connector.......Page 375
Figure 9-93 Layer stack-up for shielded dual-plane example with blind vias.......Page 376
Figure 9-94 Beginning a new project for PCB design plus simulation.......Page 377
Figure 9-96 Setting up a multipage project in Capture.......Page 378
Using off-page connectors with wires......Page 379
Figure 9-98 Multiground net connector. (a) Capture part. (b) Layout footprint.......Page 380
Setting up PSpice sources......Page 381
Figure 9-100 The digital schematic page.......Page 382
Figure 9-101 The PSpice simulation page.......Page 383
Figure 9-103 Setup for time domain analysis.......Page 384
Preparing the simulated project for Layout......Page 385
Placing parts on the bottom (back) of a board......Page 386
Figure 9-107 Layer setup in Layout.......Page 387
Through-hole and blind via setup......Page 388
Figure 9-108 Assigning specifi c vias to nets.......Page 389
Figure 9-109 Assigning specific fanout vias.......Page 390
Figure 9-110 Using the Zoom DRC to set the route box.......Page 391
Figure 9-112 Routing with blind vias and through-holes.......Page 392
Using the AutoECO to update a board from Capture......Page 393
Figure 9-115 Using the AutoECO to update the PCB from changes in Capture.......Page 394
Figure 9-116 Using the AutoECO to update changes from Capture to Layout.......Page 395
Figure 9-117 The AutoECO report.......Page 396
Figure 9-118 Forcing a padstack to connect the GND and AGND planes.......Page 397
(a) J1.3 to AGND. (b) J1.3 to GND.......Page 398
Figure 9-122 High-speed digital circuit schematic.......Page 399
Table 9-11 Bill of materials for the digital design example......Page 400
Figure 9-124 Layer stack-up for the digital example.......Page 401
Figure 9-125 Assigning via connections to planes.......Page 402
Using free vias as heat pipes......Page 403
Figure 9-127 Via Selection dialog box.......Page 404
Figure 9-128 The Add Free Via dialog box.......Page 405
Figure 9-129 Setting up a free via matrix.......Page 406
the copper area obstacle.......Page 407
Determining critical trace length of transmission lines......Page 408
Table 9-14 Net route settings from the nets spread sheet......Page 409
Figure 9-133 The completed transmission line.......Page 410
Routing curved traces......Page 411
Figure 9-136 Connecting a fl oating pin to the ground plane.......Page 412
Gate and pin swapping......Page 413
Figure 9-138 Setting pin/gate swappability.......Page 414
Figure 9-139 Take note of the swap fi le name and location.......Page 415
Stitching a ground plane with the free via matrix......Page 416
Figure 9-142 Moat on TOP defi ned with anti-copper obstacle.......Page 417
Figure 9-144 A densely stitched ground plane.......Page 418
Design cache—cleanup, replace, update......Page 419
Figure 9-147 The design cache contains a list of placed parts.......Page 420
Figure 9-148 A test point placed on a net in Layout.......Page 421
Figure 9-150 Assigning the test point property to a net.......Page 422
Table 9-17 ECO Effects legend......Page 423
Making a custom Layout technology/template fi le......Page 424
Figure 9-151 Layers spreadsheet before using the Stackup Editor.......Page 425
Figure 9-152 Layer Stackup Editor.......Page 426
Figure 9-153 Layers spreadsheet after using the Stackup Editor.......Page 427
Using the Stackup Editor to set up a custom technology or template fi le......Page 428
Submitting stack-up drawings with Gerber fi les......Page 429
Printing a footprint catalog from a PCB design......Page 430
Figure 10-1 The circuit design for fabrication.......Page 432
Figure 10-2 Use the Property Editor to display part information on the schematic.......Page 433
Figure 10-3 The routed board.......Page 434
Figure 10-4 Post Process Settings spreadsheet.......Page 435
processing.......Page 436
Figure 10-7 Postprocessor report.......Page 437
Setting up a user account......Page 438
Submitting Gerber fi les and requesting a quote......Page 439
Figure 10-10 Specifying the layer type and stack-up.......Page 440
Figure 10-11 Additional PCB design parameters.......Page 441
Figure 10-13 The quote.......Page 442
Nonstandard Gerber fi les......Page 443
Figure 11-1 A basic transmission line simulation circuit.......Page 444
Simulating digital transmission lines......Page 445
Figure 11-2 PSpice simulations settings.......Page 446
Figure 11-4 Simulation results for a critical-length line (k = 2).......Page 447
Simulating analog signals......Page 448
Figure 11-6 Modifying the Bill of Materials list to include COMPGROUP.......Page 449
Using the SPECCTRA Autorouter with Layout......Page 450
Figure 11-9 Starting the SPECCTRA autorouter.......Page 451
Figure 11-10 Launching SPECCTRA from Layout.......Page 452
Figure 11-12 Launching the autorouter.......Page 453
Figure 11-14 The circuit autorouted by SPECCTRA.......Page 454
Figure 11-16 The SPECCTRA-routed board in Layout.......Page 455
Figure 11-18 SPECCTRA Route Mode view.......Page 456
Figure 11-20 Placement Setup dialog box.......Page 457
Opening a Layout-generated Gerber fi le with GerbTool......Page 458
Figure 11-22 A .GTD fi le opened with GerbTool.......Page 459
Figure 11-24 Setup Layers toolbar button.......Page 460
Figure 11-26 Making a layer the active layer.......Page 461
Figure 11-27 Import drill data.......Page 462
Figure 11-28 Look for thruhole.tap drill fi le.......Page 463
Panelization......Page 464
Using the IPC-7351 Land Pattern Viewer......Page 470
Figure 11-36 The Panelize dialog box.......Page 469
Figure 11-35 Change fi lm box size.......Page 468
Figure 11-34 Panelized PCBs. (a) Tab-routed. (b) V-scored.......Page 467
Figure 11-31 The design fi le with the imported drill data.......Page 466
Figure 11-40 Selecting a library.......Page 471
Figure 11-41 Selecting a search category.......Page 472
Using CAD Tools to 3-D Model a PCB......Page 473
Figure 11-44 Flat board representation in Layout.......Page 474
Figure 11-45 3-D CAD model of the PCB.......Page 475
Appendix A Layout Technology Files......Page 476
IPC Standards......Page 478
MIL-STD......Page 479
Table C-1 A List of Package Abbreviations (Continued)......Page 480
Table C-2 A List of Common Discrete Component Packages......Page 482
Table C-3 Discrete Package (DPAK)......Page 483
Table C-4 Some of the Small Outline Transistor (SOT/SSOT/SC) Packages......Page 484
Table C-5 Some of the Small Outline Integrated Circuit (SOIC/SOP/SO) Packages......Page 486
Table C-7 A List of Ball Grid Array Standards (Continued)......Page 487
Table C-8 A List of Quad Flat Packs Standards......Page 488
Table C-9 A List of Some Quad Flat Packs–No Lead (QFN) Standards......Page 489
Appendix D Rise and Fall Times for Various Logic Families......Page 492
Table E-1 English Sizes......Page 494
Table E-2 Metric Sizes (mm)......Page 495
Component Package Types and Mounting (SMD)......Page 496
Layer Stack-ups......Page 497
Dielectric (relative permittivity) properties......Page 498
PCB......Page 499
Assembly types......Page 500
Lead-to-hole ratio......Page 501
Rise and Fall Times of Logic Families......Page 502
Propagation speed/time delay......Page 503
Terminations......Page 504
Noise reduction (general)......Page 505
Wave soldering......Page 506
Thermal Management......Page 507
Asymmetric stripline......Page 508
Propagation delay time......Page 509
Sharp corners......Page 510
Industry Standards......Page 512
Web Sites......Page 513
References......Page 514
Index......Page 516