In the world of optical data communications this book will be an absolute must-read. It focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. What’s more, it provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented.
Author(s): Paul Muller, Yusuf Leblebici
Edition: 1
Year: 2007
Language: English
Pages: 212
Table of Contents......Page 9
About the Authors......Page 6
Foreword......Page 7
Constants, Symbols and Acronyms......Page 13
CHAPTER 1: Introduction......Page 21
CHAPTER 2: Integrated Photonic Systems......Page 25
2.2 Metropolitan-Area Networks......Page 26
2.3 Local Area Networks and Short-Distance Interconnects......Page 27
2.4 Optical Backplane Technology......Page 29
2.5 Optical on-chip Interconnects......Page 30
CHAPTER 3: Basic Concepts......Page 32
3.2 NRZ Random Data......Page 34
3.3 Clock Recovery Basics......Page 37
3.5 System Bandwidth and Inter-Symbol Interference......Page 38
3.6 Amplitude Noise......Page 40
3.7.1 Jitter Contributions......Page 41
3.7.3 Regenerators and Retiming Repeaters......Page 43
3.8 Multichannel Systems......Page 44
3.9 Definition of Transistor-Level Conventions......Page 45
3.9.1 Large-Signal Model......Page 46
3.9.2 Small-Signal Model......Page 47
CHAPTER 4: System-Level Specifications......Page 48
4.1 Technology......Page 49
4.2 System-Level Requirements......Page 51
4.3 Receiver System Specifications......Page 52
4.4 Subblock Parameters......Page 54
4.5 Transimpedance Amplifier Analysis......Page 55
4.5.1 Transfer Function......Page 56
4.5.2 Noise Model......Page 58
4.5.3 Specification of Design Parameters......Page 60
4.6 System Gain and Bandwidth Specifications......Page 61
4.7 Bit Error Ratio Evaluation......Page 62
4.7.1 Vertical Eye Closure Contribution......Page 63
4.7.2 Horizontal Eye Closure Contribution......Page 66
4.7.3 Combined Horizontal–Vertical Eye Closure Estimation......Page 68
4.8 Block Specification Flow......Page 72
5.1 Photodetection......Page 75
5.2 PIN Photodiodes......Page 77
5.3 Avalanche Photodiodes......Page 78
5.4 Differential N-Well Detector......Page 79
5.5 Equalized PIN Detector......Page 81
5.6.1 The Resonant Cavity Structure......Page 83
5.6.2 Distributed Bragg Reflectors......Page 84
5.6.3 Detector Fabrication......Page 85
5.8 Lateral Photodetectors......Page 88
5.9 Photodetector Characterization......Page 89
6.1 Principles of I-V Conversion......Page 91
6.2.1 Common-Gate Input Stage Amplifiers......Page 94
6.2.2 Voltage Amplifier Based TIAs......Page 95
6.2.3 Source Follower Output Stages......Page 97
6.2.4 Topology Discussion......Page 98
6.4.1 Description of the TIA Amplifier......Page 100
6.4.2 Design Procedure......Page 101
6.4.3 DC Compensation......Page 103
6.4.4 Complete Block Diagram......Page 105
6.4.5 Input Noise Estimation......Page 107
6.5.1 Channel Constraints......Page 109
6.6.1 Frequency-Domain Measurements......Page 110
6.6.2 Time-Domain Measurements......Page 111
7.1 Principles of Signal Limiting......Page 112
7.2.1 Cascade of Gain Stages......Page 114
7.2.3 Group Delay......Page 115
7.2.4 Basic Gain Stage......Page 116
7.3.1 Inductive Peaking......Page 117
7.3.2 Active Inductors......Page 118
7.3.3 Capacitive Degeneration......Page 119
7.3.5 The Cherry–Hooper Amplifier......Page 120
7.3.6 Active Feedback Structure......Page 123
7.3.8 Topology Discussion......Page 124
7.5.1 Interstage Scaling Optimization......Page 125
7.5.3 Discussion......Page 128
7.6.1 The Inductor......Page 129
7.6.2 Magnetic Coupling Coefficient......Page 130
7.6.3 Design of the Amplifier Core......Page 132
7.6.4 Discussion......Page 133
7.7.1 Offset Compensation......Page 134
7.7.3 Limiting Amplifier Noise Estimation......Page 136
7.8 Block Layout......Page 137
7.9.1 Measurement Setup for Time-Domain Measurements......Page 138
7.9.2 Eye Diagram Measurements......Page 140
7.9.3 Magnetic Coupling Measurements......Page 141
7.10 Discussion......Page 142
CHAPTER 8: Clock and Data Recovery Circuit......Page 144
8.1 Clock Recovery Principles......Page 145
8.1.1 NRZ Data Phase Detection......Page 147
8.1.2 Linear Phase Detector......Page 148
8.1.3 Binary Phase Detector......Page 150
8.2 CDR Topologies......Page 152
8.2.1 PLL-Based Topologies......Page 153
8.2.2 DLL-Based Topologies......Page 154
8.2.3 Oversampling Receivers......Page 155
8.2.4 Phase Interpolation......Page 156
8.2.5 Injection Locking......Page 158
8.2.6 Gated Oscillator Topology......Page 159
8.3 Topology Discussion......Page 160
8.5 The Gated Oscillator Topology......Page 161
8.5.2 The Clock Recovery Core......Page 162
8.5.3 CDR Top-Down Design Methodology......Page 166
8.6 Statistical Modeling of the Gated Oscillator......Page 167
8.6.1 Jitter Statistics......Page 168
8.6.2 Random Jitter Components......Page 169
8.6.3 Deterministic Jitter Components......Page 170
8.6.4 Sinusoidal Jitter Model......Page 171
8.6.5 Bathtub Curves and BER Estimation......Page 175
8.7.1 CDR Model......Page 178
8.7.2 Input Data Source with Extended Jitter Model......Page 180
8.7.3 Duration of Edge Detection Pulse......Page 186
8.8.1 Current-Mode Logic Cells......Page 187
8.8.2 Low-Power CDR Design......Page 189
8.8.3 Scaling Theory......Page 191
8.9.1 Eye Diagram Measurements......Page 193
8.9.2 Bit Error Ratio Measurements......Page 194
8.10 Discussion......Page 197
CHAPTER 9: Conclusions......Page 198
References......Page 199
D......Page 205
O......Page 206
W......Page 207
