* Practical, hands-on approach to CMOS layout theory and design * Offers engineers and technicians the training materials they need to stay current in circuit design technology * Covers manufacturing processes and their effect on layout and design decisions * Includes sections on database management, project scheduling, layout audits, and chip finishing * Discusses CAD software tools used in CMOS IC layout processes * Covers both theory and application of CMOS IC layout basic and advanced skills, allowing readers to apply the book's content to everyday work projects.CMOS IC Layout: Concepts, Methodologies, and Tools is designed to train technicians and circuit designers on the practical layout of CMOS ICs. Currently companies that specialize in IC development and production, like Motorola, AMD, Intel, etc., have trouble hiring circuit designers without a tremendous investment in training, or else paying top dollar for experienced designers. CMOS IC Layout will solve these problems by bridging the gap between theory and application.This book includes basic methodologies, review of basic electrical rules and how they apply, design rules, IC planning, detailed checklists for design review, specific layout design flows, specialized block design, interconnect design, and also additional information on design limitations due to production requirements.
Author(s): Dan Clein
Series: Newnes
Publisher: Newnes
Year: 1999
Language: English
Pages: 281
Tags: Приборостроение;Полупроводниковые приборы;Интегральные схемы;
Contents......Page 6
Preface......Page 7
Acknowledgments......Page 13
1.1 History of the profession......Page 17
1.2 What is layout design?......Page 18
1.3 IC design flow......Page 20
2.1 The MOS transistor: the basic circuit structure......Page 23
2.2 Logic gates......Page 26
2.3 Transmission gates......Page 32
2.4 Understanding the schematic connectivity......Page 33
2.5 Review of fundamental electrical laws......Page 34
3.1 Introduction to CMOS VLSI manufacturing processes......Page 38
3.2 Layers and connectivity......Page 39
3.3 Introduction to transistor layout......Page 44
3.4 Process design rules......Page 51
3.5 Vertical connection diagram......Page 57
3.6 A general procedure to follow......Page 58
3.7 Preparing to start......Page 59
3.8 General guidelines......Page 66
3.9 Implementing the design......Page 75
3.10 Verification......Page 79
3.11 Final steps......Page 81
4.1 What is a flow?......Page 84
4.2 Microprocessor design flow......Page 87
4.3 ASSPs......Page 89
4.4 Memories......Page 93
4.5 System on a chip, or SOC......Page 94
4.6 CAD tools as part of a flow......Page 95
5.1 Standard cell libraries......Page 107
5.2 Special logic cells......Page 123
5.3 Pad cells......Page 130
5.4 Memory design leaf cells......Page 139
5.5 Laser fuse cells......Page 145
5.6 Chip finishing cells......Page 148
6 Advanced techniques for building-block interconnect layout design......Page 153
6.1 Power grid......Page 154
6.2 Clock signals......Page 157
6.3 Interconnect routing......Page 159
7.1 Resistance......Page 170
7.2 Capacitance......Page 175
7.3 Symmetry......Page 185
7.4 Special electrical requirements......Page 191
8.1 Wide metal slits......Page 199
8.2 Large metal via implementations......Page 202
8.3 Step coverage rules......Page 203
8.4 Multiple rule sets......Page 205
8.5 Antenna rules......Page 207
8.6 Special design rules......Page 208
8.7 Latch-up......Page 211
9.1 Layout of circuits design for change......Page 217
9.2 Planning for unknown changes......Page 223
9.3 Engineering change orders......Page 227
9.4 Guidelines for proper layout......Page 229
10.1 Introduction......Page 232
10.2 Planning tools......Page 235
10.3 Layout generation tools......Page 240
10.4 Support tools......Page 252
A1 Cells......Page 261
A2 Blocks......Page 262
A3 Chips......Page 264
Appendix B Database management......Page 265
Appendix C Scheduling......Page 270
Index......Page 273
