Covering the essentials of analog circuit design, this book takes a unique design approach based on a MOSFET model valid for all operating regions, rather than the standard square-law model. Opening chapters focus on device modeling, integrated circuit technology, and layout, whilst later chapters go on to cover noise and mismatch, and analysis and design of the basic building blocks of analog circuits, such as current mirrors, voltage references, voltage amplifiers, and operational amplifiers. An introduction to continuous-time filters is also provided, as are the basic principles of sampled-data circuits, especially switched-capacitor circuits. The final chapter then reviews MOSFET models and describes techniques to extract design parameters. With numerous design examples and exercises also included, this is ideal for students taking analog CMOS design courses and also for circuit designers who need to shorten the design cycle.
Author(s): Márcio Cherem Schneider, Carlos Galup-Montoro
Edition: 1
Year: 2010
Language: English
Pages: 506
Title......Page 5
Copyright......Page 6
Dedication......Page 7
Contents......Page 9
Preface......Page 17
1.1.1. The need for analog design......Page 21
1.1.3. The importance of component modeling......Page 22
1.2.1. p–n Junctions......Page 23
1.2.2. Bipolar junction transistors......Page 25
1.2.3. MOS field-effect transistors......Page 27
1.2.4. Important differences between BJTs and MOSFETs......Page 34
1.3.1. Analysis and design of integrated circuits......Page 36
1.3.2. Design of common-emitter and common-source amplifiers......Page 37
Problems......Page 41
References......Page 44
2.1.1 Electrons and holes in semiconductors......Page 46
2.1.2 The two-terminal MOS structure......Page 48
2.1.2.1 The flat-band voltage......Page 50
2.1.3 Accumulation, depletion, and inversion (for p-type substrates)......Page 51
2.1.4 The small-signal equivalent circuit of the two-terminal MOS (for p-type substrates)......Page 52
2.1.5 The three-terminal MOS structure and the unified charge-control model (UCCM)......Page 54
2.1.6 The pinch-off voltage......Page 58
2.1.7 The Pao–Sah exact I-V model......Page 59
2.1.9 A charge-control compact model......Page 61
2.1.10 Threshold voltage......Page 62
2.2.1 Forward and reverse components of the drain current......Page 65
2.2.2 Universal dc characteristics......Page 68
2.2.3 MOSFET operation in weak and strong inversion......Page 71
2.2.4 Small-signal transconductances......Page 73
2.3.1 Stored charges......Page 77
2.3.2 Capacitive coefficients......Page 79
2.3.4 A non-quasi-static small-signal model......Page 82
2.3.5 A quasi-static small-signal model......Page 85
2.3.6 The intrinsic transition frequency......Page 87
2.4.1 Effective mobility......Page 88
2.4.2 Velocity saturation......Page 89
2.4.3 Channel-length modulation......Page 91
2.4.4 Drain-induced barrier lowering......Page 92
2.4.5 Output conductance in saturation......Page 93
2.4.6 Gate tunneling currents......Page 95
2.4.7 Bulk current......Page 96
A2.1 Semiconductor charges......Page 97
A2.2 Drain- and source-associated inversion charges......Page 99
A2.4 An alternative low-frequency small-signal model of the MOSFET in saturation......Page 101
Problems......Page 104
References......Page 106
3.1.1 Basic process steps in monolithic IC fabrication......Page 108
3.1.2.1 Transistor fabrication......Page 109
3.1.2.2 MOSFET structure in deep-submicron processes......Page 111
3.1.3 Main parameters in 350- 180- and 90-mm processes......Page 112
3.2 Devices in CMOS technology......Page 113
3.2.1 Resistors......Page 114
3.2.1.1 Polysilicon resistors......Page 116
3.2.1.2 Implanted and diffused resistors......Page 118
3.2.1.3 The MOS transistor as a resistor......Page 120
3.2.2 Capacitors......Page 121
3.2.2.1 Metal–insulator–metal (MIM) capacitors......Page 122
3.2.2.2 Metal–oxide–semiconductor (MOS) capacitors......Page 124
3.2.2.3 MOSFET gate capacitors......Page 126
3.2.3 Inductors......Page 129
3.2.4 Bipolar transistors......Page 132
3.3 Latchup......Page 134
3.4.1 Optical lithography......Page 135
3.4.2 Mask layout and design rules......Page 138
3.4.3.1 Layout for matching......Page 141
3.4.3.2 Folded layout......Page 144
3.4.3.4 Series association of transistors......Page 145
Problems......Page 148
References......Page 150
4.1.1 Thermal noise......Page 154
4.1.3 Flicker noise......Page 156
4.2. Modeling the drainurrent fluctuations in MOSFETs......Page 157
4.3.1 Channel thermal noise......Page 159
4.3.2 Shorth-channel effects on channel thermal noise......Page 160
4.3.3 Induced gate noise......Page 161
4.4 Flicker noise in MOSFETs......Page 164
4.5.2 The thermal noise excess factor......Page 167
4.5.3 Flicker noise in terms of inversion levels......Page 168
4.5.4 The corner frequency......Page 170
4.5.5.1 The correlation admittance......Page 171
4.5.5.2 MOS-transistor equivalent input noise generators......Page 172
4.6 Systematic and random mismatch......Page 174
4.6.1 Pelgrom’s model of mismatch......Page 175
4.6.2 (Mis)matching energy......Page 181
4.6.3 The number-fluctuation mismatch model......Page 182
4.6.4 The dependence of mismatch on bias, dimensions, and technology......Page 184
4.6.5.1 Monte Carlo simulation......Page 187
4.6.5.2 Small-signal analysis of the mismatch sensitivity of a circuit......Page 189
Problems......Page 190
References......Page 195
5.1.2 The two-transistor current mirror......Page 197
5.1.3 Error caused by difference between drain voltages......Page 199
5.1.4 Error caused by transistor mismatch......Page 200
5.1.5 Small-signal characterization and frequency response......Page 204
5.1.6 Noise......Page 206
5.2 Cascode current mirrors......Page 207
5.2.1 Self-biased cascode current mirrors......Page 208
5.2.2 High-swing cascode current mirrors......Page 209
5.3 Advanced current mirrors......Page 211
5.4 Class-AB current mirrors......Page 212
A.5.1 Harmonic distortion......Page 213
Problems......Page 215
References......Page 218
6.1 A simple MOS current source......Page 219
6.2 The Widlar current source......Page 220
6.3 Self-biased current sources (SBCSs)......Page 221
6.4 A MOSFET-only self-biased current source......Page 225
6.5 Bandgap voltage references......Page 228
6.5.1 The operating principle of the bandgap reference......Page 229
6.5.2 CMOS bandgap references......Page 230
6.5.3 A CMOS bandgap reference with sub-1-V operation......Page 234
6.5.4 A resistorless CMOS bandgap reference......Page 236
6.6 CMOS voltage references based on weighted VGS......Page 237
6.7 A current-calibrated CMOS PTAT voltage reference......Page 238
Problems......Page 239
References......Page 242
7.1.1 Resistive load......Page 245
7.1.2 Diode-connected load......Page 246
7.1.3 The intrinsic gain stage......Page 248
7.1.4 Current source load......Page 251
7.1.5 The push–pull amplifier (static CMOS inverter)......Page 256
7.2 Common-gate amplifiers......Page 259
7.3 Source followers......Page 262
7.4.1 Telescopic-and folded-cascode amplifiers......Page 266
7.4.2 The gain-boost technique......Page 270
7.5.1 The source-coupled pair......Page 272
7.5.1.1 The dc transfer characteristics......Page 273
7.5.1.2 The common-mode input range......Page 274
7.5.1.3 The input offset voltage......Page 275
7.5.1.4 Small-signal analysis......Page 276
7.5.2 Resistive-load differential amplifiers......Page 279
7.5.3.1 Voltage transfer characteristics......Page 280
7.5.3.2 The common-mode input range......Page 281
7.5.3.4 The offset voltage......Page 282
7.5.3.5 Small-signal analysis – differential voltage gain......Page 284
7.5.3.6 Small-signal analysis – common-mode gain and CMRR......Page 286
7.5.3.7 Small-signal analysis – power-supply rejection ratio......Page 291
7.5.3.8 Noise......Page 293
7.5.3.9 The slew rate and settling response......Page 295
7.6 Sizing and biasing of MOS transistors for amplifier design......Page 298
7.6.1 Sizing and biasing of a common-source amplifier......Page 299
7.6.2 The design procedure for a common-source amplifier......Page 300
7.6.3 MOSVIEW: a graphical interface for MOS transistor design......Page 301
7.7 Reuse of MOS analog design......Page 303
7.7.1 Effects of scaling on analog circuits......Page 304
7.7.2.1 Constant-inversion-level scaling......Page 305
7.7.2.2 Channel-length scaling: L→L/KL......Page 306
7.7.2.3 A design-reuse example......Page 307
Problems......Page 308
References......Page 310
8.1.1 The ideal operational amplifier......Page 312
8.1.2 Basic applications of operational amplifiers......Page 313
8.1.3 Performance parameters......Page 317
8.2.1 The simple-stage differential amplifier......Page 319
8.2.2 The telescopic-cascode differential amplifier......Page 321
8.3.1 DC characteristics......Page 322
8.3.2 Small-signal characteristics and noise......Page 324
8.3.3 Slew rate......Page 325
8.4.1 DC characteristics......Page 326
8.4.2 Small-signal characteristics and noise......Page 328
8.4.3 Slew rate......Page 332
8.5.1 Cascade versus cascode amplifiers......Page 340
8.5.2 DC characteristics of the two-stage amplifier......Page 341
8.5.3 Small-signal characteristics of the two-stage Miller-compensated op amp......Page 342
8.5.4 Slew rate......Page 354
8.5.5.1 Elimination of the feedforward effect of CC using a buffer......Page 356
8.5.5.2 Elimination of the feedforward effect of CC using a common-gate amplifier......Page 357
8.5.5.3 A nulling resistor......Page 358
8.6 Three-stage operational amplifiers......Page 359
8.7 Rail-to-rail input stages......Page 360
8.8 Class-AB output stages for operational amplifiers......Page 362
8.9 Fully-differential operational amplifiers......Page 370
A8.1 Systematic offset of a two-stage op amp......Page 379
Problems......Page 380
References......Page 383
9.1 Basics of MOSFET-C filters......Page 386
9.1.1 The MOSFET as a tunable resistor......Page 387
9.1.2 Balanced transconductors for MOSFET-C filters......Page 388
9.1.3 MOSFET-C integrators......Page 390
9.1.4 Filter examples......Page 396
9.2 Basics of OTA-C filters......Page 398
9.2.1 Transconductors......Page 399
9.2.2 Gm-C integrators......Page 403
9.2.3 Signal-to-noise ratio, dynamic range, and power......Page 406
9.2.4 Filter examples......Page 410
9.3 Digitally-programmable continuous-time filters......Page 413
9.4 On-chip tuning schemes......Page 415
A9.1 Distortion of the MOSFET operating as a resistor......Page 417
Problems......Page 419
References......Page 420
10.1.1 Sample-and-hold basics......Page 424
10.1.2 Thermal noise......Page 426
10.1.3 Switch on-resistance......Page 429
10.1.4 Sampling distortion due to switch on-resistance......Page 430
10.1.5 Linearization of the MOS sampling switch......Page 432
10.1.6 Charge injection by the switch......Page 433
10.1.6.1 Reducing injection errors......Page 435
10.1.6.2 Rejecting injection errors......Page 436
10.1.7 Low-voltage sample-and-hold circuits......Page 437
10.1.8 Jitter analysis......Page 441
10.1.9 Tradeoff between resolution and sampling rate in analog-to-digital converters......Page 442
10.2.1 Basic principles of operation of switched-capacitor circuits......Page 443
10.2.2 Switched-capacitor integrators......Page 446
10.2.3 Offset compensation......Page 449
10.2.4 Biquad filters......Page 450
10.2.5 Amplifier specifications......Page 453
10.2.6 Low-distortion switched-capacitor filters......Page 455
10.3 Switched-capacitor circuits as charge processors......Page 457
10.3.1 Realization of linear voltage processors......Page 458
10.3.2 Implementation issues......Page 460
10.4 Alternative switched-circuit techniques......Page 461
A10.1 Modeling the sampling distortion due to the non-finearity of the switch on-resistance......Page 464
Problems......Page 466
References......Page 470
11.1 MOSFET models for circuit simulation......Page 472
11.1.1 Threshold-voltage-based models (BSIM3 and BSIM4)......Page 473
11.1.2 Surface-potential-based models (HiSIM, MM11, and PSP)......Page 474
11.1.2.2 The MOS Model 11......Page 476
11.1.3 Charge-based models (EKV, ACM, and BSIM5)......Page 478
11.1.3.2 The ACM model......Page 479
11.2 Parameter extraction for first-order design......Page 480
11.2.1 Specific current and threshold voltage......Page 481
11.2.2 The slope factor......Page 483
11.2.3 Mobility......Page 485
11.3 Comparison between experiment and the ACM model in a 0.35-μm technology......Page 487
11.4 Comparison between simulation and the ACM model in a 0.13-µm technology......Page 490
11.5 The Early voltage......Page 493
Problems......Page 499
References......Page 500
Index......Page 503
