Chiplet Design and Heterogeneous Integration Packaging

Preface
Acknowledgments
Contents
About the Author
1 State-Of-The-Art of Advanced Packaging
1.1 Introduction
1.2 Flip-Chip Bumping and Bonding/Assembly
1.2.1 Flip-Chip Bumping
1.2.2 Flip-Chip Bonding/Assembly
1.3 Hybrid Bonding
1.3.1 Some Fundamental on Hybrid Bonding
1.3.2 Sony’s CIS with Hybrid Bonding
1.3.3 TSMC’s Hybrid Bonding
1.3.4 Intel’s Hybrid Bonding
1.3.5 SK Hynix’s Hybrid Bonding
1.4 2D IC Integration
1.5 2.1D IC Integration
1.5.1 Thin-Film Layers on Package Substrates
1.5.2 Fine Metal L/S RDL Bridge Embedded in Organic Package Substrate
1.5.3 Fine Metal L/S RDL Bridge Embedded in Fan-Out EMC
1.5.4 Fine Metal L/S RDL Flexible Bridge
1.6 3D IC Integration
1.6.1 SAP/PCB Method
1.6.2 Fan-Out with Chip-First Method
1.6.3 Fan-Out with Chip-Last Method
1.7 2.5D IC Integration
1.7.1 AMD/UMC’s 2.5D IC Integration
1.7.2 NVidia/TSMC’s 2.5D IC Integration
1.7.3 Some Recent Advances in 2.5D IC Integration
1.8 3D IC Integration
1.8.1 3D IC Packaging (Without TSVs)
1.8.2 3D IC Integration (with TSVs)
1.9 Chiplet Design and Heterogeneous Integration Packaging
1.9.1 System on Chip (SoC)
1.9.2 Chiplet Design and Heterogeneous Integration Packaging
1.9.3 Advantages and Disadvantages
1.9.4 Xilinx’s Chiplet Design and Heterogeneous Integration Packaging
1.9.5 AMD’s Chiplet Design and Heterogeneous Integration Packaging
1.9.6 CEA Leti’s Chiplet Design and Heterogeneous Integration Packaging
1.9.7 Intel’s Chiplet Design and Heterogeneous Integration Packaging
1.9.8 TSMC’s Chiplet Design and Heterogeneous Integration Packaging
1.10 Fan-In Packaging
1.10.1 Six-Side Molded WLCSP
1.10.2 Reliability of WLCSP: Conventional Versus Six-Side Molded
1.11 Fan-Out Packaging
1.12 Dielectric Materials for Advanced Packaging
1.12.1 Why Need Low Dk and Df Dielectric Materials?
1.12.2 Why Need Low CTE Dielectric Materials?
1.13 Summary and Recommendation
References
2 Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration
2.1 Introduction
2.2 DARPA’s Efforts in Chipet Heterogeneous Integration
2.3 SoC (System-On-Chip)
2.4 Chiplet Design and Heterogeneous Integration Packaging
2.5 Advantages and Disadvantages of Chiplet Design and Heterogeneous Integration Packaging
2.6 Xilinx’s Chiplet Design and Heterogeneous Integration Packaging
2.7 AMD’s Chiplet Design and Heterogeneous Integration Packaging
2.8 Intel’s Chiplet Design and Heterogeneous Integration Packaging
2.9 TSMC’s Chiplet Design and Heterogeneous Integration Packaging
2.10 Graphcore’s Chiplet Design and Heterogeneous Integration Packaging
2.11 CEA-LETI’s Chiplet Design and Heterogeneous Integration Packaging
2.12 UCIe (Universal Chiplet Interconnect Express)
2.13 Summary and Recommendations
References
3 Multiple System and Heterogeneous Integration with TSV-Interposers
3.1 Introduction
3.2 Through-Silicon Via (TSV)
3.2.1 Tiny Vias on a Chip
3.2.2 TSV (Via-First Process)
3.2.3 TSV (Via-Middle Process)
3.2.4 TSV (Via-Last from the Front-Side Process)
3.2.5 TSV (Via-Last from the Back-Side Process)
3.3 Passive TSV-Interposers Versus Active TSV-Interposers
3.4 Active TSV-Interposer Fabrication
3.5 Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)
3.5.1 UCSB/AMD’s Multiple System and Heterogeneous Integration with Active TSV-Interposer
3.5.2 Intel’s Multiple System and Heterogeneous Integration with Active TSV-Interposers
3.5.3 AMD’s Multiple System and Heterogeneous Integration with Active TSV-Interposers
3.5.4 CEA-Leti’s Multiple System and Heterogeneous Integration with Active TSV-Interposers
3.6 Passive TSV-Interposer Fabrication
3.6.1 Fabrication of TSVs
3.6.2 Fabrication of RDLs
3.6.3 Fabrication of RDLs: Polymer + Cu-Plating and Etching Method
3.6.4 Fabrication of RDLs: SiO2 + Cu Damascene and CMP Method
3.6.5 A Note on Contact Aligner for Cu Damascene Method
3.6.6 Backside Processing and Assembly
3.7 Multiple System and Heterogeneous Integration with Passive TSV-Interposers (2.5D IC Integration)
3.7.1 CEA-Leti’s SoW (System-on-Wafer)
3.7.2 TSMC’s CoWoS (Chip-on-Wafer-on-Substrate)
3.7.3 Xilinx/TSMC’s Multiple System and Heterogeneous Integration
3.7.4 Altera/TSMC’s Multiple System and Heterogeneous Integration
3.7.5 AMD/UMC’s Multiple System and Heterogeneous Integration
3.7.6 NVidia/TSMC’s Multiple System and Heterogeneous Integration
3.7.7 TSMC’s Multiple System and Heterogeneous Integration with DTC
3.7.8 Samsung’s Multiple System and Heterogeneous Integration with Integrated Stack Capacitor (ISC)
3.7.9 Graphcore’s Multiple System and Heterogeneous Integration
3.7.10 Fujitsu’s Multiple System and Heterogeneous Integration
3.7.11 Samsung’s Multiple System and Heterogeneous Integration (I-Cube4)
3.7.12 Samsung’s Multiple System and Heterogeneous Integration (H-Cube)
3.7.13 Samsung’s Multiple System and Heterogeneous Integration (MIoS)
3.7.14 IBM’s Multiple System and Heterogeneous Integration (TCB)
3.7.15 IBM’s Multiple System and Heterogeneous Integration (Hybrid Bonding)
3.7.16 Multiple System and Heterogeneous Integration of EIC and PIC (Side-by-Side)
3.7.17 Multiple System and Heterogeneous Integration of EIC and PIC (3D Stacked)
3.7.18 Fraunhofer’s Multiple System and Heterogeneous Integration with Glass-Interposer
3.7.19 Fujitsu’s Multiple System and Heterogeneous Integration with Glass-Interposer
3.7.20 Dai Nippon/AGC’s Multiple System and Heterogeneous Integration with Glass-Interposer
3.7.21 GIT’s Multiple System and Heterogeneous Integration with Glass-Interposer
3.7.22 Leibniz University Hanover/Ulm University’s Electroless Glass Interposer
3.7.23 Summary and Recommendations
3.8 Heterogeneous Integration with Stacked TSV Interposers
3.8.1 Module Construction
3.8.2 Thermo-Mechanical Design
3.8.3 Carrier Fabrication
3.8.4 Thin Wafer Handling
3.8.5 Module Assembly
3.8.6 Module Reliability Assessment
3.8.7 Summary and Recommendations
3.9 Multiple System and Heterogeneous Integration with TSV Interposers
3.9.1 The Structure
3.9.2 TSV Etching and CMP
3.9.3 Thermal Measurement
3.9.4 Thin-Wafer Handling
3.9.5 Microbumping, C2W Assembly, and Reliability Assessment
3.9.6 Failure Mechanism of 20 μm Pitch Micro Solder Joints
3.9.7 Electromigration in Solder Micro Joints
3.9.8 Final Structure
3.9.9 Leakage Current Issue
3.9.10 Thermal Simulation and Measurement of the Structure
3.9.11 Summary and Recommendations
3.10 Multiple System and Heterogeneous Integration with Chips on Both-Side of TSV Interposers
3.10.1 The Structure
3.10.2 Thermal Analysis—Boundary Conditions
3.10.3 Thermal Analysis—TSV Equivalent Model
3.10.4 Thermal Analysis—Solder Bump/Underfill Equivalent Model
3.10.5 Thermal Analysis—Results
3.10.6 Thermomechanical Analysis—Boundary Conditions
3.10.7 Thermomechanical Analysis—Material Properties
3.10.8 Thermomechanical Analysis—Results
3.10.9 Fabrication of the TSV
3.10.10 Fabrication of the Interposer with Topside RDLs
3.10.11 TSV Reveal of the Cu-Filled Interposer with Topside RDLs
3.10.12 Fabrication of the Interposer with Bottom-Side RDLs
3.10.13 Passive Electrical Characterization of the Interposer
3.10.14 Final Assembly
3.10.15 Summary and Recommendations
3.11 Multiple System and Heterogeneous Integration with Through-Silicon Hole
3.11.1 Electrical Simulation and Results
3.11.2 Test Vehicle
3.11.3 Top Chip with UBM/PAD and Cu Pillar
3.11.4 Bottom Chip with UBM/Pad/Solder
3.11.5 TSH Interposer
3.11.6 Final Assembly
3.11.7 Reliability Assessments
3.11.8 Summary and Recommendations
References
4 Multiple System and Heterogeneous Integration with TSV-Less Interposers
4.1 Introduction
4.2 Fan-Out Technology
4.2.1 Chip-First with Die Face-Down
4.2.2 Chip-First with Die Face-Up
4.2.3 Die Shift Issues
4.2.4 Warpage Issues
4.2.5 Chip-Last (RDL-First)
4.2.6 Heterogeneous Integration of EIC and PIC Devices
4.2.7 Antenna-In-Package (AiP)
4.3 Patent Issue
4.4 2.3D IC Integration with Fan-Out (Chip-First) Packaging
4.4.1 Fan-Out (Chip-First) Packaging
4.4.2 STATSChipPac’s 2.3D eWLB (Chip-First)
4.4.3 MediaTek’s Fan-Out (Chip-First)
4.4.4 ASE’s FOCoS (Chip-First)
4.4.5 TSMC’s InFO_oS and InFO_MS (Chip-First)
4.5 2.3D IC Integration with Fan-Out (Chip-Last) Packaging
4.5.1 NEC/Renesas’ Fan-Out (Chip-Last or RDL-First) Packaging
4.5.2 Amkor’s SWIFT (Chip-Last)
4.5.3 Samsung’s Si-Less RDL Interposer (Chip-Last)
4.5.4 TSMC’s Multilayer RDL Interposer (Chip-Last)
4.5.5 ASE’s FOCoS (Chip-Last)
4.5.6 SPIL’s Large Size Fan-Out Chip-Last 2.3D
4.5.7 Shinko’s 2.3D Organic Interposer (Chip-Last)
4.5.8 Samsung’s Cost-Effective 2.3D Packaging (Chip-Last)
4.5.9 Unimicron’s 2.3D IC Integration (Chip-Last)
4.6 Other 2.3D IC Integration Structures
4.6.1 Shinko’s Coreless Organic Interposer
4.6.2 Intel’s Knights Landing
4.6.3 Cisco’s Coreless Organic Interposer
4.6.4 Amkor’s SLIM
4.6.5 Xilinx/SPIL’s SLIT
4.6.6 SPIL’s NTI
4.6.7 Samsung’s TSV-Less Interposer
4.7 Summary and Recommendations
4.8 2.3D IC Heterogeneous Integration with ABF
4.8.1 The Structure
4.8.2 Test Chips
4.8.3 Wafer Bumping
4.8.4 Fine Metal L/S/H RDL-Substrate (Organic Interposer)
4.8.5 Build-Up Package Substrate
4.8.6 Warpage Measurements
4.8.7 Hybrid Substrate
4.8.8 Final Assembly
4.8.9 Finite Element Simulation and Results
4.8.10 Summary and Recommendations
4.9 2.3D IC Heterogeneous Integration with Interconnect-Layer
4.9.1 The Structure
4.9.2 Test Chips
4.9.3 Fine Metal L/S RDL-Interposer
4.9.4 Interconnect-Layer
4.9.5 HDI PCB
4.9.6 Final Assembly of the Hybrid Interposer
4.9.7 Characterizations of the Hybrid Substrate
4.9.8 Final Assembly
4.9.9 Reliability Assessment
4.9.10 Summary and Recommendations
4.10 Characterization of Low-Loss Dielectric Materials for 2.3D IC Heterogeneous Integration
4.10.1 Why Low-Loss Dielectric?
4.10.2 Raw Materials and Their Data Sheets
4.10.3 Sample Preparation
4.10.4 Fabry–Perot Open Resonator (FPOR)
4.10.5 Test Vehicle Designed by Polar and ANSYS
4.10.6 Test Vehicles Fabrication
4.10.7 TDR Measurement and Results
4.10.8 Effective Dielectric Constant (Ɛeff)
4.10.9 VNA Measurement and Correlation with Simulation Results
4.10.10 Summary and Recommendations
References
5 Chiplets Lateral Communications
5.1 Introduction
5.2 Rigid Bridges Versus Flexible Bridges
5.3 Intel’s EMIB
5.3.1 Solder Bumps for EMIB
5.3.2 Fabrication of EMIB Substrate
5.3.3 Bonding Challenges for EMIB
5.4 IBM’s DBHi
5.4.1 Solder Bumps for DBHi
5.4.2 DBHi Bonding Assembly
5.4.3 DBHi Underfilling
5.4.4 DBHi Challenges
5.5 Université de Sherbrooke/IBM’s Self-aligned Bridge
5.5.1 Process Flow of the V-Groove Opening of the Self-aligned Bridge
5.5.2 Measurement Results
5.5.3 Challenges of Self-aligned Bridge
5.6 Patents on Rigid Bridges with Fan-Out Packaging
5.7 TSMC’s LSI
5.8 SLIP’s FO-EB and FO-EB-T
5.8.1 FO-EB
5.8.2 FO-EB-T
5.9 ASE’s sFOCoS
5.9.1 The Structure and Process of sFOCoS
5.9.2 The Structure and Process of FOCoS-CL
5.9.3 Reliability and Warpage Between sFOCoS and FOCoS-CL
5.10 Amkor’s S-Connect
5.10.1 S-Connect with Si-Bridge
5.10.2 S-Connect with Molded RDL-Bridge
5.11 IME’s EFI
5.11.1 Process Flow of EFI
5.11.2 Thermal Performance of EFI
5.12 imec’s Bridge
5.12.1 The Structure of imec’s Bridge
5.12.2 The Process of imec’s Bridge
5.12.3 The Challenges of imec’s Bridge
5.13 UCIe Consortium
5.14 Flexible Bridge
5.15 Unimicron’s Hybrid Bonding Bridge
5.15.1 Hybrid Bonding Bridge with C4 Bumps on the Package Substrate
5.15.2 Hybrid Bonding Bridge with C4 Bumps on the Chiplet Wafer
5.16 Summary and Recommendations
References
6 Cu-Cu Hybrid Bonding
6.1 Introduction
6.2 Direct Cu-Cu TCB
6.2.1 Some Fundamental on Direct Cu-Cu TCB
6.2.2 IBM/RPI’s Cu-Cu TCB
6.3 Direct SiO2-SiO2 TCB
6.3.1 Some Fundamental on SiO2-SiO2 TCB
6.3.2 MIT’s SiO2-SiO2 TCB
6.3.3 Leti/Freescale/STMicroelectronics’ SiO2-SiO2 TCB
6.4 A Brief History of Cu-Cu Hybrid Bonding
6.5 Some Fundamental on Cu-Cu Hybrid Bonding
6.6 Sony’s Direct Cu-Cu Hybrid Bonding
6.6.1 Sony’s CIS with Oxide-Oxide TCB
6.6.2 Sony’s CIS with Cu-Cu Hybrid Bonding
6.6.3 Sony’s Three-Wafer Hybrid Bonding
6.6.4 Sony’s Bond Strength on W2W Hybrid Bonding
6.7 SK Hynix’s Cu-Cu Hybrid Bonding
6.7.1 Hybrid Bonding for DRAM Applications
6.7.2 Bonding Yield Improvement
6.8 Samsung’s Cu-Cu Hybrid Bonding
6.8.1 Characterization of Hybrid Bonding
6.8.2 Effect of Pad Structure and Layout on Hybrid Bonding
6.8.3 Voids in Cu-Cu Hybrid Bonding
6.8.4 CoW Hybrid Bonding of 12-Momery Stacked
6.9 TEL’s Cu-Cu Hybrid Bonding
6.9.1 Simulation of Hybrid Bonding
6.9.2 Wet Atomic Layer Etch of Cu
6.10 Tohoku’s Cu-Cu Bonding
6.10.1 Cu Grain Enlargement
6.10.2 Hybrid Bonding with Cu/PI Systems
6.11 Imec’s Cu-Cu Hybrid Bonding
6.11.1 Hybrid Bonding with Cu/SiCN Surface Topography
6.11.2 Die-To-Wafer Hybrid Bonding
6.11.3 Thermal and Mechanical Reliability of Hybrid Bonding
6.12 CEA-LETI’s Cu-Cu Hybrid Bonding
6.12.1 CEA-LETI/ams Cu-Free Hybrid Bonding
6.12.2 CEA-LETI/SET D2W Hybrid Bonding
6.12.3 CEA-LETI/Intel D2W Self-assembly for Hybrid Bonding
6.13 IME’s Cu-Cu Hybrid Bonding
6.13.1 Simulation of SiO2 W2W Hybrid Bonding
6.13.2 Simulation of SiO2 C2W Hybrid Bonding
6.13.3 Simulation of Cu/Polymer C2W Hybrid Bonding
6.13.4 Yield Improvement on C2W Hybrid Bonding
6.14 Intel’s Cu-Cu Hybrid Bonding
6.15 Xperi’s Cu-Cu Hybrid Bonding [51–57]
6.15.1 D2W Hybrid Bonding—Die Size Effect
6.15.2 Multi-Die Stacks with Hybrid Bonding
6.16 Applied Material’s Cu-Cu Hybrid Bonding
6.16.1 Dielectric Materials for Hybrid Bonding
6.16.2 Development Platform for Hybrid Bonding
6.17 Mitsubishi’s Cu-Cu Hybrid Bonding
6.18 Unimicron’s Hybrid Bonding
6.19 D2W vs. W2W Hybrid Bonding
6.20 Summary and Recommendation
References
Index