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PREFACE
Purpose of This Manual
Intended Audience
Manual Contents
What’s New in This Manual
Technical or Customer Support
Supported Processors
Product Information
MyAnalog.com
Processor Product Information
Related Documents
Online Technical Documentation
Accessing Documentation From VisualDSP++
Accessing Documentation From Windows
Accessing Documentation From the Web
Printed Manuals
VisualDSP++ Documentation Set
Hardware Tools Manuals
Processor Manuals
Data Sheets
Conventions
INTRODUCTION
Manual Organization
Blackfin Processor Instruction Set Reference
Syntax Conventions
Case Sensitivity
Free Format
Instruction Delimiting
Comments
Notation Conventions
Behavior Conventions
Glossary
Register Names
Functional Units
Arithmetic Status Flags
Fractional Convention
Saturation
Rounding and Truncating
Automatic Circular Addressing
PROGRAM FLOW CONTROL
Instruction Overview
Jump
IF CC JUMP
Call
RTS, RTI, RTX, RTN, RTE (Return)
LSETUP, LOOP
Blackfin Processor Instruction Set Reference
LOAD / STORE
Instruction Overview
Load Immediate
Load Pointer Register
Load Data Register
Load Half-Word – Zero-Extended
Load Half-Word – Sign-Extended
Load High Data Register Half
Load Low Data Register Half
Load Byte – Zero-Extended
Load Byte – Sign-Extended
Store Pointer Register
Store Data Register
Store High Data Register Half
Store Low Data Register Half
Store Byte
MOVE
Instruction Overview
Move Register
Move Conditional
Move Half to Full Word – Zero-Extended
Move Half to Full Word – Sign-Extended
Move Register Half
Blackfin Processor Instruction Set Reference
Move Byte – Zero-Extended
Move Byte – Sign-Extended
STACK CONTROL
Instruction Overview
-SP (Push)
-SP (Push Multiple)
SP++ (Pop)
SP++ (Pop Multiple)
LINK, UNLINK
CONTROL CODE BIT MANAGEMENT
Instruction Overview
Compare Data Register
Compare Pointer
Compare Accumulator
Move CC
Negate CC
LOGICAL OPERATIONS
Instruction Overview
& (AND)
~ (NOT One’s Complement)
| (OR)
^ (Exclusive-OR)
BXORSHIFT, BXOR
Blackfin Processor Instruction Set Reference vii
BIT OPERATIONS
Instruction Overview
BITCLR -2
BITSET
BITTGL
BITTST
DEPOSIT
EXTRACT
BITMUX
ONES (One’s Population Count)
SHIFT/ROTATE OPERATIONS
Instruction Overview
Add with Shift
Shift with Add
Arithmetic Shift
Logical Shift
ROT (Rotate)
ARITHMETIC OPERATIONS
Instruction Overview
ABS
Add
Add/Subtract – Prescale Down
Add/Subtract – Prescale Up
Blackfin Processor Instruction Set Reference
Add Immediate
DIVS, DIVQ (Divide Primitive)
EXPADJ
MAX
MIN
Modify – Decrement
Modify – Increment
Multiply 16-Bit Operands
Multiply 32-Bit Operands
Multiply and Multiply-Accumulate to Accumulator
Multiply and Multiply-Accumulate to Half-Register
Multiply and Multiply-Accumulate to Data Register
Negate (Two’s Complement)
RND (Round to Half-Word)
Saturate
SIGNBITS
Subtract
Subtract Immediate
EXTERNAL EVENT MANAGEMENT
Instruction Overview
Idle
Core Synchronize
System Synchronize
EMUEXCPT (Force Emulation)
Blackfin Processor Instruction Set Reference ix
Disable Interrupts
Enable Interrupts
RAISE (Force Interrupt / Reset)
EXCPT (Force Exception)
Test and Set Byte (Atomic)
No Op
CACHE CONTROL
Instruction Overview
PREFETCH
FLUSH
FLUSHINV
IFLUSH
VIDEO PIXEL OPERATIONS
Instruction Overview
ALIGN8, ALIGN16, ALIGN24
DISALGNEXCPT
BYTEOP3P (Dual 16-Bit Add / Clip)
Dual 16-Bit Accumulator Extraction with Addition
BYTEOP16P (Quad 8-Bit Add)
BYTEOP1P (Quad 8-Bit Average – Byte)
BYTEOP2P (Quad 8-Bit Average – Half-Word)
BYTEPACK (Quad 8-Bit Pack)
BYTEOP16M (Quad 8-Bit Subtract)
Blackfin Processor Instruction Set Reference
SAA (Quad 8-Bit Subtract-Absolute-Accumulate)
BYTEUNPACK (Quad 8-Bit Unpack)
VECTOR OPERATIONS
Instruction Overview
Add on Sign
VIT_MAX (Compare-Select)
Vector ABS
Vector Add / Subtract
Vector Arithmetic Shift
Vector Logical Shift
Vector MAX
Vector MIN
Vector Multiply
Vector Multiply and Multiply-Accumulate
Vector Negate (Two’s Complement)
Vector PACK
Vector SEARCH
ISSUING PARALLEL INSTRUCTIONS
Supported Parallel Combinations
Parallel Issue Syntax
32-Bit ALU/MAC Instructions
16-Bit Instructions
Examples
Blackfin Processor Instruction Set Reference xi
