Biomedical Electronics, Noise Shaping ADCs, and Frequency References: Advances in Analog Circuit Design 2022

Preface
The Topics Covered Before in This Series
Contents
Part I Biomedical Electronics
Overview of Design Challenges in High-Performance ExG Interfaces
1 Progress in Biomedical Systems
2 Challenges in Design of ExG Readouts
2.1 Electrode Offsets and CMOS Integration
2.1.1 Problem Description
2.1.2 Existing Solutions
2.1.3 Summary
2.2 Power Supply Interference and Common-Mode Rejection
2.2.1 Problem Description
2.2.2 Existing Solutions
2.2.3 Summary
2.3 High Input Impedance for Use with Dry Electrodes
2.3.1 Problem Description
2.3.2 Existing Solutions
2.3.3 Summary
2.4 Cabling Complexity and Patient Mobility
2.4.1 Problem Description
2.4.2 Existing Solutions
2.4.3 Summary
2.5 Low-Noise Design for Power- and Area-Efficient Systems
2.5.1 Problem Description
2.5.2 Existing Solutions
3 Conclusions
References
VCO-Based ADCs for Direct Digitization of ExG Signals
1 Introduction
2 ExG Biosignals
3 Acquisition Circuits
4 VCO-Based ADCs
4.1 The VCO as an Integrator
4.2 Quantizer
4.2.1 XOR-Based FDC
4.2.2 Counter-Based FDC
4.3 Properties of VCO-Based ADCs
4.3.1 First-Order Noise Shaping and Anti-aliasing
4.3.2 Linearity
4.3.3 Resilience to Metastability
4.4 ExG VCO-Based AFE Literature Survey
5 A Second-Order VCO-Based ExG Interface
5.1 ADC Architecture
5.1.1 Basic Operation
5.2 Design of a Mimatch Resilient Quantizer
5.3 Multi-quantizer Structure
5.4 Chopping and Impedance Boosting
5.5 Architecture Summary
5.6 Measurement Results
5.6.1 Electrical Characterization
5.6.2 Biological Measurements
6 Conclusions
References
Circuits and Architectures for Neural Recording Interfaces
1 Introduction
2 Neural Readout Architectures
2.1 IA-ADC Readout Architectures
2.2 Direct-to-Digital Readout Architectures
2.2.1 Recording-Only Architectures
2.2.2 Artifact-Tolerant Architectures for Bidirectional Neural Interfaces
2.3 Performance Benchmarking
3 Conclusions
References
Chip-Integrated Spin Detection for Biomedical Applications
1 Motivation
2 Introduction to NMR
3 EPR for Biomedical Applications
4 Chip-Integrated NMR and EPR Electronics
4.1 Transceiver Architectures for NMR-on-a-Chip Detectors
4.2 Oscillator-Based EPR
5 Chip-Integrated Dynamic Nuclear Polarization
6 Summary and Conclusion
References
Models and Interfaces for Electrochemical Sensors: Architectures and Implementations
1 Introduction
2 Chemical Sensor and Electrochemical Sensor Overview
3 Electrode-Electrolyte Interface and Electrochemical Sensor Systems
3.1 Electrode-Electrolyte Interface
3.2 The Electrochemical Sensor System
4 Typical Electrochemical Techniques
4.1 Potentiometric Analysis
4.2 Coulometric Analysis
4.3 Voltammetric Analysis
4.4 Electrochemical Impedance Spectroscopy (EIS)
5 Electrical Modeling of the Electrochemical Sensor
5.1 Modeling of the Electrode-Electrolyte Interface
5.2 Modeling of the Two-Electrode System
5.3 Modeling of the Three-Electrode Sensor System
6 Typical Electrochemical Sensor System Interface Architectures
6.1 Example 1: Op-Amp-Based Potentiostat+TIA
6.2 Example 2: Current Mirror-Based Potentiostat+Current-to-Frequency Converter
7 Future Trends
8 Conclusions
References
Next-Generation Molecular Detection with a CMOS Capacitive Sensor
1 Introduction
2 Molecular Detection Methods
2.1 Antigen and Antibody Lateral Flow Devices
2.2 DNA Sequencing
2.3 PCR Testing
2.4 LAMP/Isothermal Testing
3 Biosensors
3.1 Electrochemical Glucose Sensor
3.2 Electrochemical DNA Sensor
3.3 Capacitive DNA Biosensors
3.4 Magnetic Bead GMR Biosensor
4 CMOS Biosensors
4.1 The ISFET
4.2 ISFET DNA Detection and Ion Semiconductor Sequencing
4.3 CMOS Hall Sensor Biochip
4.4 CMOS Capacitive DNA Biosensor
4.5 CMOS Bioluminescence Assay Sensor
5 The PNA-BeadCAP® Molecular Detection Assay
5.1 PNA Probes
5.2 BeadCAP® Capacitance Detection Method and Circuits
6 Discussion and Conclusions
References
Part II Noise-Shaping ADCs
The Evolution of Noise-Shaping SuccessiveApproximation (SAR) ADC
1 Introduction
2 SAR ADC
3 Noise-Shaping SAR Basics
4 Implementation
4.1 The First NS SAR: A CIFF Implementation
4.2 EF Implementation
5 Cascaded Noise Shaping
6 Hybrid CT Converters with NS SAR Quantizers
7 Interleaved Noise-Shaping SAR
8 Conclusions
References
Noise-Shaped SAR ADCs: Current Trends and Challenges
1 Introduction
2 Summation
2.1 Charge-Based Summation
2.2 Current-Based Summation
3 Loop Filter Topologies
3.1 Error Feedback (EF)
3.2 Cascade of Integrators Feedforward (CIFF)
4 Trends in NS SAR
5 Ease of Drive and Power Considerations
5.1 Multi-sampling Approach
5.2 Pre-charge Techniques
6 kT/C Suppression
7 DAC Element Mismatch
7.1 Mismatch Error Shaping
7.2 Calibration-Based Techniques
8 Dynamic Amplifiers
9 Conclusions
References
Noise-Shaping SAR ADCs: From Discrete Time to Continuous Time
1 Introduction
2 Discrete-Time Noise-Shaping SAR ADC
2.1 Loop Filter
2.2 Mismatch Error Shaping
2.3 Measurement Results
3 Continuous-Time Noise-Shaping SAR ADC
3.1 Architecture
3.2 Measurement Results
4 Discussion
5 Conclusion
References
The Zoom ADC: An Evolving Architecture
1 Introduction
2 System-Level Design of the Zoom ADC
2.1 Asynchronous SAR ADC
2.2 SQNR Recovery
2.3 SAR Quantization Noise Leakage
3 Amplifiers in DT Zoom ADCs
4 Continuous-Time Zoom ADCs
4.1 Amplifiers in CT Zoom ADCs
4.2 DAC Drivers
4.3 Example: A CT Zoom ADC with a Coarse NS SAR
5 Conclusions
References
Pushing the Limits of kT/C Noise in Delta-Sigma Modulators
1 Introduction to kT/C Noise
2 Introduction to the FoMS and Current State-of-the-Art Trends
3 The 192 dB FoMS Boundary
4 kT/C Noise Cancellation: Previous Work
5 Delta-Sigma Modulators: General Overview
6 Introducing CGA Stage to Delta-Sigma Modulators
7 Theoretical Analysis of the CGA Stage
8 Impact of the CGA on the SNR Performance of Delta-Sigma Modulators
9 Conclusions
References
A Second-Order 5bit Hybrid CT/DT Delta-Sigma ADC Implementing Novel Techniques for ELD Compensation and Coefficient Trimming
1 Introduction
2 ADC Architecture
3 ADC Block Description
3.1 Loop Filter
3.2 SAR Quantizer
3.3 Resistive Feedback DAC
4 ELD Compensation
5 Coefficients' Self-Trim Procedure
6 Measurement Results
7 Conclusions
References
Part III Frequency References
RC Frequency References Based on Dual RC FLLs
1 Introduction
2 Dual RC Frequency-Locked Loop
2.1 Basic FLL Architecture
2.2 Modified FLL Using Phase Information
2.3 Phase Digitizer Based on Phase-Domain Δ Modulator
2.4 Digital Temperature Compensation for FLLs
2.5 Dual RC Frequency Reference
3 Implementation and Measurement Results
3.1 Digital Phase-Domain Delta-Sigma Modulator
3.2 Digitally Controlled Oscillators
3.3 Measurement Results
4 Conclusions
References
RC Oscillators with Non-linear Temperature Compensation
1 Introduction
2 R-RC Oscillator for Second Order
3 Non-linearity-Aware Dual Phase-Locked Loop
4 Conclusion
References
RC Frequency References Based on Pulse-Density Trimmed Resistors
1 Introduction
2 First-Order Temperature-Compensated Oscillator
2.1 Second-Order Compensated Reference Resistor
2.2 Design Considerations
2.2.1 Finite Capacitance at SCR's Switching Node
2.2.2 Incomplete Settling of SCR Internal Nodes
2.2.3 Finite Off Resistance of SCR Switches
2.2.4 Finite Off Resistance of Switched Resistors
2.2.5 Integrator Offset
2.2.6 Frequency-Locked Loop Design
2.3 Trimming Procedure
2.4 Circuit Implementation
2.5 Measurement Results
2.5.1 Performance with Two-Point Trim
2.5.2 Performance with Three-Point Trim
2.5.3 Output Clock Performance
3 Conclusions
References
Integrated BAW-Based Frequency References
1 Introduction
2 Bulk Acoustic Wave Resonators
2.1 Passive Temperature Compensation
2.2 Resonator Model
3 BAW Oscillator Topologies
3.1 Oscillation Modes
3.2 Phase Noise
4 Active Temperature Compensation
4.1 Frequency Adjustment
5 Frequency Error
6 Advantages of BAW Oscillators
6.1 High PLL Reference Frequency
6.2 Fast Startup
6.3 Robustness
6.4 Security
7 Other Uses for BAW Oscillators
7.1 BAW to Replace RF Synthesizer
7.2 BAW as a Jitter Cleaner
7.3 BAW as a Temperature Sensor
8 Conclusions
References
MEMS Oscillators Revolutionizing the Precision Timing Market
1 Introduction
2 MEMS OSC Architecture
3 DualMEMS™ TDC
4 Stability Signal Chain
5 Measurement Results
6 Introducing the Elite-X Platform
7 Conclusions
References
Fast Startup and Fully Differential Crystal Oscillator
1 Introduction
2 Fast Startup
2.1 Energy in a Crystal During Oscillation
2.2 Theoretical Minimum Startup Time
2.3 Synchronizing the Block Wave to the Crystal Current
3 Differential Crystal Oscillator
3.1 Differential Switched Capacitor Crystal Oscillator
3.2 PSRR Improvement by Correlated Sampling
4 Measurement Results
4.1 Fast Startup
4.2 Phase Noise
4.3 Performance Summary (Table 1)
5 Conclusions
References
Index