Asynchronous Circuit Applications

Cover
Contents
About the editors
1 Introduction
1.1 Overview of asynchronous circuits
1.2 Advantages of asynchronous circuits
1.3 Overview of asynchronous circuit applications
References
2 Asynchronous circuits for dynamic voltage scaling
2.1 Introduction
2.2 Block-level asynchronous circuits
2.2.1 Quasi-delay-insensitive (QDI) sub-threshold self-adaptive VDD scaling (SSAVS)
2.2.1.1 SSAVS system design
2.2.1.2 Precharged-static-logic (PCSL)
2.2.1.3 Block-level QDI asynchronous FRM FB
2.2.1.4 Circuit realization and measurement results
2.2.2 Pseudo-quasi-delay-insensitive sub-threshold self-adaptive VDD scaling (SSAVS)
2.2.2.1 Asynchronous pseudo-QDI realization approach
2.2.2.2 Timing analysis on the proposed pseudo-QDI realization approach
2.2.2.3 Circuit realization and measurement results
2.3 Gate-level asynchronous circuits
2.3.1 Sense-amplifier half buffer (SAHB)
2.3.2 Design example: Kogge–Stone (KS) 64-bit adder embodying SAHB
2.4 Conclusions
References
3 Power-performance balancing of asynchronous circuits
3.1 Pipelining the asynchronous design
3.1.1 Pipeline balancing
3.1.2 Pipeline dependency
3.2 The parallel architecture and its control scheme
3.2.1 DVS for the homogeneous platform
3.2.2 Pipeline latency and throughput detection
3.2.3 Pipeline fullness and voltage mapping
3.2.4 Workload prediction
3.2.5 Circuit fabrication and measurement
3.3 Advanced topics on power-performance balancing
3.3.1 Homogeneous platform with core disability
3.3.1.1 Core disabling and enabling sequence
3.3.1.2 Fine-grained core state control
3.3.2 Architecture of the heterogeneous platform
3.3.2.1 Multiplexer and demultiplexer design with NULL cycle reduction
3.3.2.2 Asynchronous arbiter design
3.3.2.3 Platform cascading
3.4 Conclusion
References
4 Asynchronous circuits for ultra-low supply voltages
4.1 Introduction
4.1.1 Subthreshold operation and FDSOI process technology
4.1.2 NULL conventional logic and multithreshold NULL conventional logic
4.2 Asynchronous and synchronous design
4.2.1 Synchronous and asynchronous (NCL) ring oscillator
4.2.2 Synchronous FIR filter
4.2.3 Asynchronous (MTNCL) FIR filter
4.2.4 MTNCL homogeneous parallel asynchronous platform
4.3 Physical testing methodologies
4.4 Physical testing results
4.4.1 Synchronous designs
4.4.2 Asynchronous designs
4.5 Conclusion
References
5 Asynchronous circuits for interfacing with analog electronics
5.1 The ring oscillator metaphor
5.2 Example applications
5.2.1 An asynchronous serializer/deserializer utilizing a full-duplex RS-485 link
5.2.2 Fully asynchronous successive approximation analog to digital converters
5.2.2.1 Basic operation of the successive approximation analog-to-digital converter
5.2.2.2 Asynchronous input voltage sampling
5.2.2.3 Asynchronous voltage comparisons
5.3 Conclusion
References
6 Asynchronous sensing
6.1 Image sensors
6.1.1 Frames versus frameless sensing
6.1.2 Traditional (synchronous) image sensors
6.1.3 Asynchronous spiking pixel sensors
6.1.4 Asynchronous logarithmic sensors
6.2 Sensor processors
6.2.1 SNAP: a sensor-network asynchronous processor
6.2.2 BitSNAP
6.3 Signal processing
6.3.1 Continuous-time DSP
6.3.2 Asynchronous analog-to-digital converters
6.3.3 A hybrid synchronous–asynchronous FIR filter
6.4 Conclusion
References
7 Design and test of high-speed asynchronous circuits
7.1 How fast can a self-timed circuit run?
7.1.1 Logic gate delays
7.1.2 Rings of logic gates
7.1.3 Amplifying pulse signals
7.1.4 The theory of logical effort, or how to make fast circuits
7.1.5 Summary and conclusion of Section 7.1
7.2 The Link and Joint model
7.2.1 Communication versus computation
7.2.2 Initialization and test
7.2.2.1 Action control: go and MrGO
7.2.3 Summary and conclusion of Section 7.2
7.3 The Weaver, an 8 x 8 crossbar experiment
7.3.1 Weaver architecture and floorplan
7.3.1.1 Crossbar switch
7.3.1.2 Steering bits
7.3.1.3 Test infrastructure: scan, counters, and reloaders
7.3.2 Weaver circuits
7.3.2.1 First-in-first-out (FIFO) circuits
7.3.2.2 Critical path: latches to data kiting to double-barrel Links
7.3.2.3 Crossbar circuits: Splitter, Double-barrel Ricochet, Crosser
7.3.3 Test logistics
7.3.3.1 Scan chains and connections to Weaver Links and Joints
7.3.4 How low-speed scan chains test high-speed performance
7.3.5 Performance measurements
7.3.5.1 Throughput versus occupancy at nominal power supply
7.3.5.2 Throughput for various power supply voltages
7.3.5.3 Power for various power supply voltages
7.3.5.4 Power for various data patterns
7.3.6 Summary and conclusion of Section 7.3
References
8 Asynchronous network-on-chips (NoCs) for resource efficient many core architectures
8.1 Basics of asynchronous NoCs
8.1.1 Mesochronous architectures
8.1.2 Plesiochronous architectures
8.1.3 Heterochronous architectures
8.1.4 Asynchronous architectures
8.2 GALS extensions for embedded multiprocessors
8.2.1 State-of-the art of GALS-based NoC-architectures
8.2.2 The CoreVA-MPSoC
8.2.3 Mesochronous router implementation
8.2.4 Asynchronous router implementation
8.2.5 Design-space exploration of the different GALS-approaches
8.2.5.1 Power consumption
8.2.5.2 Latency and throughput
8.2.5.3 Global clock tree
8.3 Conclusion
References
9 Asynchronous field-programmable gate arrays (FPGAs)
9.1 Why asynchronous FPGAs?
9.1.1 Mapping synchronous logic to standard FPGAs
9.1.2 Mapping asynchronous logic to standard FPGAs
9.2 Gate-level asynchronous FPGAs
9.2.1 Supporting synchronous and asynchronous logic
9.2.2 Supporting pure asynchronous logic
9.2.3 Supporting asynchronous templates
9.3 Dataflow asynchronous FPGAs
9.4 Discussion
References
10 Asynchronous circuits for extreme temperatures
10.1 Digital circuitry in extreme environments
10.2 Asynchronous circuits in high-temperature environments
10.2.1 High temperature NCL circuit project overview
10.2.2 High temperature NCL circuit results
10.3 Low temperature NCL circuit project overview
10.3.1 Low temperature NCL circuit project overview
10.3.2 Low temperature NCL circuit results
10.4 Conclusion
References
11 Asynchronous circuits for radiation hardness
11.1 Asynchronous architectures for mitigating SEE
11.1.1 NCL multibit SEU and data-retaining SEL architecture
11.2 Radiation hardened asynchronous NCL library and component design
11.3 Analyzing radiation hardness
References
12 Dual rail asynchronous logic design methodologies for side channel attack mitigation
12.1 Introduction
12.1.1 Side channel attacks
12.1.2 Dual-rail logic solution to SCAs
12.2 NCL SCAs mitigation capabilities and weaknesses
12.2.1 NCL balanced power consumption
12.2.2 NCL unbalanced combinational logic
12.2.3 NCL SCA mitigation
12.3 Dual-spacer dual-rail delay-insensitive logic (D3L)
12.3.1 Introducing an all-ones spacer
12.3.2 Adapting NCL register to the dual-spacer scheme
12.3.2.1 D3L ko generation
12.3.2.2 D3L ki generation
12.3.2.3 D3L filter register
12.3.2.4 D3L spacer generator register
12.3.3 D3L resilience to side channel attacks
12.4 Multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L)
12.4.1 The first MTD3L version
12.4.2 Reinvented MTD3L design methodology
12.4.2.1 Approach
12.4.2.2 Spacer generator registers elimination
12.4.2.3 Register cell transistor-level implementation
12.4.2.4 MTD3L simulation and results
12.4.2.5 Side channel attacks resilience
12.5 Results
12.6 Conclusion
References
13 Using asynchronous clock distribution networks for timing SFQ circuits
13.1 Introduction
13.1.1 Why superconductive?
13.1.2 Timing is a challenge
13.1.3 Asynchronous clock distribution networks
13.1.4 Chapter overview
13.2 Background
13.2.1 SFQ technology
13.2.2 Timing fundamentals
13.2.3 Clocking in SFQ
13.3 Asynchronous clock distribution networks
13.3.1 MG theory
13.3.2 ACDN theory
13.3.2.1 Synchronous clock sinks
13.3.2.2 Uncertainty case
13.4 Hierarchical chains of homogeneous clover-leaves clocking
13.4.1 Hierarchical chains
13.4.2 Bottom level
13.4.3 Top loop
13.4.4 (HC)2 LC theory
13.4.5 Cycle time and clock skew
13.4.6 Comparison to conventional CDN
13.5 Discussion
References
14 Uncle—Unified NCL Environment—an NCL design tool
14.1 Overview
14.2 Flow details
14.2.1 RTL specification to single-rail netlist
14.2.2 Single-rail netlist to dual-rail netlist
14.2.3 Ack network generation
14.2.4 Net buffering, latch balancing (optional steps)
14.2.5 Relaxation, ack checking, cell merging, and cycle time reporting
14.3 Example—a 16-bit GCD circuit
14.3.1 Synchronous implementation
14.3.2 Data-driven NCL implementation
14.3.3 Control-driven NCL implementation
14.4 Conclusion
References
15 Formal verification of NCL circuits
15.1 Overview of approach
15.2 Related verification works for asynchronous paradigms
15.3 Equivalence verification for combinational NCL circuits
15.3.1 Functional equivalence check
15.3.2 Invariant check
15.3.3 Handshaking check
15.3.4 Input-completeness check
15.3.4.1 Input-completeness proof obligation: NULL to DATA
15.3.4.2 Input-completeness proof obligation: DATA to NULL
15.3.4.3 Input-completeness results
15.3.5 Observability check
15.3.5.1 Observability proof obligation: NULL to DATA
15.3.5.2 Observability proof obligation: DATA to NULL
15.3.5.3 Observability results
15.4 Equivalence verification for sequential NCL circuits
15.4.1 Safety
15.4.2 Liveness
15.4.3 Sequential NCL circuit results
15.5 Conclusions and future work
References
16 Conclusion
Index
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