This book constitutes the refereed proceedings of the 22nd International Conference on Architecture of Computing Systems, ARCS 2009, held in Delft, The Netherlands, in March 2009.
The 21 revised full papers presented together with 3 keynote papers were carefully reviewed and selected from 57 submissions. This year's special focus is set on energy awareness. The papers are organized in topical sections on compilation technologies, reconfigurable hardware and applications, massive parallel architectures, organic computing, memory architectures, enery awareness, Java processing, and chip-level multiprocessing.
Author(s): Mladen Berekovic, Christian Müller-Schloer, Christian Hochberger, Stephan Wong
Series: Lecture Notes in ... Computer Science and General Issues
Edition: 1
Publisher: Springer
Year: 2009
Language: English
Pages: 269
Life on the Treadmill......Page 12
Key Microarchitectural Innovations for Future Microprocessors......Page 13
The Challenges of Multicore: Information and Mis-Information......Page 14
Introduction......Page 15
Concept......Page 16
FPGA-Based Prototype......Page 17
Annotation Primitives......Page 18
Code Transformation......Page 19
Coding Restrictions......Page 21
Support for the FPGA-Based Prototype......Page 22
Performance Measurements......Page 23
Conclusions......Page 25
Introduction......Page 27
Related Work......Page 28
Design Flow......Page 29
Problem Statement......Page 30
Experiments and Quantitative Evaluation......Page 33
Conclusions and Future Work......Page 37
Introduction......Page 39
Definitions......Page 41
Measurements......Page 42
Test Platform......Page 44
Test Results......Page 45
Conclusion......Page 49
Introduction......Page 51
Bloom Filter Data Structure......Page 52
Conventional Bloom Filter Architecture for Word Matching......Page 53
Parallel Partitioned Bloom Filter Architecture......Page 55
Performance Analysis......Page 58
References......Page 60
Introduction......Page 61
SRAM-FPGAs in Space......Page 62
Requirements for Future Space Missions......Page 63
Dynamic Partial Reconfiguration in Virtex-4 FPGA......Page 64
SpaceWire......Page 65
SoCWire CODEC......Page 67
SoCWire Switch......Page 68
Test and Results......Page 69
References......Page 70
Introduction and Motivation......Page 71
Related Work......Page 73
Runtime-Reconfigurable Function Calls......Page 74
TSS-Based Dynamic Linking System (DLS)......Page 75
GOT-Based Linking System (GLS)......Page 77
Multi-threading Considerations......Page 78
Single-Threaded Execution......Page 79
Multi-threaded Execution (OpenMP)......Page 80
Conclusion and Outlook......Page 81
Introduction......Page 83
Related Work......Page 85
Hardware Architecture......Page 88
Results......Page 91
Conclusion and Future Extensions......Page 93
Introduction......Page 95
Related Work......Page 97
Components......Page 98
Message Protocols......Page 99
Mote Side......Page 101
PC Side......Page 103
Evaluation......Page 104
Conclusion......Page 105
Introduction......Page 107
Data Parallel Architecture (DPA)......Page 109
Application: N-Body Problem......Page 111
Generated DPAs with Adapted Operators......Page 114
Conclusion......Page 116
Introduction......Page 119
Related Work and Background Knowledge......Page 120
Continuous Double Auction Based Resource Allocation......Page 121
Proposed Algorithm......Page 122
Matchmaker Promotion: Segmentation......Page 123
Matchmaker Demotion: Desegmentation......Page 124
Matchmaker Discovery......Page 125
Experimental Setup and Results......Page 126
Experimental Results......Page 128
Conclusions......Page 129
Introduction......Page 131
Related Work......Page 132
Principles of SeMCDM......Page 133
Conditions for the Allocation of the Matching Steps on Autonomous Units......Page 134
Market Scenario 1......Page 135
Simulation of the Market Scenarios......Page 136
Settings of the Application Environment......Page 137
Simulation Results of the Market Scenarios......Page 138
Recommendations......Page 143
References......Page 144
Introduction......Page 146
Parallel Computing......Page 147
Self-contained Parallel Cooperation......Page 148
Self-organized Parallel Cooperation......Page 149
Task Partitioning......Page 150
Task Scheduling......Page 151
Experiments......Page 152
Conclusions......Page 155
Introduction......Page 157
ViVA Architecture and Implementation......Page 158
Experimental Platform......Page 161
Microbenchmarks......Page 162
Compact Kernel: Corner Turn......Page 165
Compact Kernel: Sparse Matrix Vector Multiplication......Page 166
Related Work......Page 167
Summary and Conclusions......Page 168
Introduction......Page 170
Related Work......Page 172
Video Data Transfer Characteristics......Page 173
Enhanced DMA Controller Implementation......Page 174
Evaluation......Page 177
Performance Measures......Page 178
Conclusions......Page 179
Introduction......Page 182
Fine-Grained Run-Time Power Gating......Page 183
Power Domain Partition......Page 185
BET Analysis......Page 186
Dynamic Sleeping Control Policy......Page 187
Power Analysis Method......Page 189
Leakage Reduction Efficiency......Page 190
Area Overhead......Page 191
Conclusions......Page 192
Introduction......Page 194
Related Work......Page 195
DVFS on Supply Island: An Architectural View......Page 196
Energy Modeling......Page 198
Representative Traffic Patterns......Page 199
Energy Minimization......Page 201
Latency Penalty......Page 202
Conclusion and Future Work......Page 203
Introduction......Page 206
Background......Page 207
Energy Management Service......Page 209
Software Agents......Page 211
EMS Protocol......Page 212
eEMS Device Implementation and Test Scenario......Page 213
Conclusions......Page 216
References......Page 217
Introduction......Page 218
Garbage Collection for Multithreaded Multicores......Page 219
General Functionality......Page 220
Fragmentation......Page 221
The Java Core Architecture......Page 222
Interconnection and Synchronization of the MultiCore......Page 223
Evaluation......Page 224
Conclusions......Page 228
Introduction......Page 230
Preliminaries......Page 231
Multivariate Adaptive Regression Splines (MARS)......Page 232
Model Diagnostics......Page 233
Experimental Methodology......Page 234
Statistical Analyses......Page 236
Model Evaluation......Page 238
Related Work......Page 241
Summary and Outlook......Page 242
Introduction and Related Work......Page 244
Design Flow......Page 246
Modular Performance Analysis......Page 248
Parameter Estimation for Accelerators......Page 249
Selection of Optimal Configuration......Page 252
Motion JPEG Decoder......Page 253
Conclusions and Future Work......Page 255
Introduction......Page 257
The SVP Model......Page 258
Creating Families of Threads......Page 260
Chip and Processor Architecture......Page 261
L1 Caches......Page 262
Memory Architecture......Page 263
Inner Product......Page 264
The 256 Point FFT......Page 265
The 4096-Point FFT......Page 266
Conclusions......Page 267
References......Page 268
