Design a high-speed SoC while gaining a holistic view of the FPGA design flow and overcoming its challenges.
Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You'll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner.
This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design.
You'll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration.
By the end of this book, you'll have learned the concepts underlying FPGA SoCs' advanced features and you'll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.
Key Features:
- Use development tools to implement and verify an SoC, including ARM CPUs and the FPGA logic
- Overcome the challenge of time to market by using FPGA SoCs and avoid the prohibitive ASIC NRE cost
- Understand the integration of custom logic accelerators and the SoC software and build them
What You Will Learn:
- Understand SoC FPGAs' main features, advanced buses and interface protocols
- Develop and verify an SoC hardware platform targeting an FPGA-based SoC
- Explore and use the main tools for building the SoC hardware and software
- Build advanced SoCs using hardware acceleration with custom IPs
- Implement an OS-based software application targeting an FPGA-based SoC
- Understand the hardware and software integration techniques for SoC FPGAs
- Use tools to co-debug the SoC software and hardware
- Gain insights into communication and DSP principles in FPGA-based SoCs
Who this book is for:
This book is for FPGA and ASIC hardware and firmware developers, IoT engineers, SoC architects, and anyone interested in understanding the process of developing a complex SoC, including all aspects of the hardware design and the associated firmware design. Prior knowledge of digital electronics, and some experience of coding in VHDL or Verilog and C or a similar language suitable for embedded systems will be required for using this book. A general understanding of FPGA and CPU architecture will also be helpful but not mandatory.
About the Author
Mounir Maaref lives in the UK and works as a Principal SoC Architect. He has 25 years' experience in the microelectronics industry spanning FPGAs, ASICs, embedded processing, networking, data storage, satellite communications, Bluetooth, and WiFi connectivity. He likes working on cutting edge technologies involving both hardware and soft ware. His main focus is on the system architecture design, hardware and software interactions, performance analysis, and modeling. He has published several application notes and white papers and has been a speaker at many conferences worldwide. He holds a masters degree in Electronics and Telecoms. He is a 2nd dan black belt in Tang Soo Do and is getting trained to become a martial arts instructor.
Author(s): Mounir Maaref
Edition: 1
Publisher: Packt Publishing
Year: 2022
Language: English
Commentary: True PDF
Pages: 426
Cover
Title Page
Copyright page
Contributors
Table of Contents
Preface
Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
Chapter 1: Introducing FPGA Devices and SoCs
Xilinx FPGA devices overview
A brief historical overview
FPGA devices and penetrated vertical markets
An overview of the Xilinx FPGA device families
An overview of the Xilinx FPGA devices features
Xilinx SoC overview and history
A short survey of the Xilinx SoC FPGAs based on an ARM CPU
Xilinx Zynq-7000 SoC family hardware features
Zynq-7000 SoC APU
Zynq-7000 SoC memory controllers
Zynq-7000 I/O peripherals block
Zynq-7000 SoC interconnect
Xilinx Zynq Ultrascale+ MPSoC family overview
Zynq UltraScale+ MPSoC APU
Zynq UltraScale+ MPSoC RPU
Zynq UltraScale+ MPSoC GPU
Zynq UltraScale+ MPSoC VCU
Zynq UltraScale+ MPSoC PMU
Zynq UltraScale+ MPSoC DMA channels
Zynq UltraScale+ MPSoC memory interfaces
Zynq-UltraScale+ MPSoC IOs
Zynq UltraScale+ MPSoC IOP block
Zynq-UltraScale+ MPSoC interconnect
SoC in ASIC technologies
High-level design steps of an SoC in an ASIC
Summary
Questions
Chapter 2: FPGA Devices and SoC Design Tools
Technical requirements
FPGA hardware design flow and tools overview
FPGA hardware design flow
FPGA hardware design tools
FPGA SoC hardware design tools
Using the Vivado IP Integrator to create a sample SoC hardware
FPGA and SoC hardware verification flow and associated tools
Adding the cross-triggering debug capability to the FPGA SoC design
FPGA SoC software design flow and associated tools
Vitis IDE embedded software design flow overview
Vitis IDE embedded software design terminology
Vitis IDE embedded software design steps
Summary
Questions
Chapter 3: Basic and Advanced On-Chip Buses and Interconnects
On-chip buses and interconnects overview
On-chip bus overview
On-chip interconnects
ARM AMBA interconnect protocols suite
ARM AMBA standard historical overview
APB bus protocol overview
AXI bus protocol overview
AXI Stream bus protocol overview
ACE bus protocol overview
OCP interconnect protocol
OCP protocol overview
OCP bus characteristics
OCP bus interface signals
OCP bus-supported transactions
DMA engines and data movements
IP-integrated DMA engines overview
IP-integrated DMA engines topology and operations
Standalone DMA engines overview
Central DMA engines topology and operations
Data sharing and coherency challenges
Data access atomicity
Cache coherency overview
Summary
Questions
Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects
Legacy off-chip interconnects overview
SPI overview
Zynq-7000 SoC SPI controller overview
I2C overview
Zynq-7000 SoC I2C controller overview
Introduction to the PCIe interconnect
Historical overview of the PCIe interconnect
PCIe interconnect system topologies
PCIe protocol layers
PCIe controller example
PCIe subsystem data exchange protocol example using DMA
PCIe system performance considerations
Ethernet interconnect
Ethernet speeds historical evolution
Ethernet protocol overview
Ethernet interface of the Zynq-7000 SoC overview
Introduction to the Gen-Z protocol
Gen-Z protocol architectural features
SoC design and Gen-Z fabric
CCIX protocol and off-chip data coherency
CCIX protocol architectural features
Summary
Questions
Chapter 5: Basic and Advanced SoC Interfaces
Interface definition by function
SoC interface characteristics
SoC interface quantitative considerations
Processor cache fundamentals
Processor cache organization
Processor MMU fundamentals
Memory and storage interface topology
DDR memory controller
Static memory controller
On-chip memory controller
Summary
Questions
Part 2: Implementing High-Speed SoC Designs in an FPGA
Chapter 6: What Goes Where in a High-Speed SoC Design
The SoC architecture exploration phase
SoCs PS processors block features
Memory and storage interfaces
Communication interfaces
PS block dedicated hardware functions
FPGA SoC device general characteristics
SoC hardware and software partitioning
A simple SoC example – an electronic trading system
Hardware and software interfacing and communication
Data path models of the ETS
Introducing the Semi-Soft algorithm
Using the Semi-Soft algorithm approach in the Zynq-based SoCs
Using system-level alternative solutions
Introduction to OpenCL
Exploring FPGA partial reconfiguration as an alternative method
Early SoC architecture modeling and the golden model
System modeling using Accellera SystemC and TLM2.0
System modeling using Synopsys Platform Architect
System modeling using the gem5 framework
System modeling using the QEMU framework and SystemC/TLM2.0
Summary
Questions
Chapter 7: FPGA SoC Hardware Design and Verification Flow
Technical requirements
Installing the Vivado tools on a Linux VM
Installing Oracle VirtualBox and the Ubuntu Linux VM
Installing Vivado on the Ubuntu Linux VM
Developing the SoC hardware microarchitecture
The ETS SoC hardware microarchitecture
Design capture of an FPGA SoC hardware subsystem
Creating the Vivado project for the ETS SoC
Configuring the PS block for the ETS SoC
Adding and configuring the required IPs in the PL block for the ETS SoC
Understanding the design constraints and PPA
What is the PPA?
Synthesis tool parameters affecting the PPA
Specifying the synthesis options for the ETS SoC design
Implementation tool parameters affecting the PPA
Specifying the implementation options for the ETS SoC design
Specifying the implementation constraints for the ETS SoC design
SoC hardware subsystem integration into the FPGA top-level design
Verifying the FPGA SoC design using RTL simulation
Customizing the ETS SoC design verification test bench
Hardware verification of the ETS SoC design using the test bench
Implementing the FPGA SoC design and FPGA hardware image generation
ETS SoC design implementation
ETS SoC design FPGA bitstream generation
Summary
Questions
Chapter 8: FPGA SoC Software Design Flow
Technical requirements
Major steps of the SoC software design flow
ETS SoC XSA archive file generation in the Vivado IDE
ETS SoC software project setup in Vitis IDE
ETS SoC MicroBlaze software project setup in the Vitis IDE
ETS SoC PS Cortex-A9 software project setup in the Vitis IDE
Setting up the BSP, boot software, drivers, and libraries for the software project
Setting up the BSP for the ETS SoC MicroBlaze PP application project
Setting up the BSP for the ETS SoC Cortex-A9 core0 application project
Setting up the BSP for the ETS SoC boot application project
Defining the distributed software microarchitecture for the ETS SoC processors
A simplified view of the ETS SoC hardware microarchitecture
A summary of the data exchange mechanisms for the ETS SoC Cortex-A9 and the MicroBlaze IPC
The ETMP protocol overview
The ETS SoC system address map
The Ethernet MAC and its DMA engine software control mechanisms
The AXI INTC software control mechanisms
Quantitative analysis and system performance estimation
The ETS SoC Cortex-A9 software microarchitecture
The ETS SoC MicroBlaze PP software microarchitecture
Building the user software applications to initialize and test the SoC hardware
Specifying the linker script for the ETS SoC projects
Setting the compilation options and building the executable file for the Cortex-A9
Summary
Questions
Chapter 9: SoC Design Hardware and Software Integration
Technical requirements
Connecting to an FPGA SoC board and configuring the FPGA
The emulation platform for running the embedded software
Using QEMU in the Vitis IDE with the ETS SoC project
Using the emulation platform for debugging the SoC test software
Embedded software profiling using the Vitis IDE
Summary
Questions
Part 3: Implementation and Integration Of Advanced High-Speed FPGA SoCs
Chapter 10: Building a Complex SoC Hardware Targeting an FPGA
Technical requirements
Building a complex SoC subsystem using Vivado IDE
System performance analysis and the system quantitative studies
Addressing the system coherency and using the Cortex-A9 ACP port
Overview of the Cortex-A9 CPU ACP in the Zynq-7000 SoC FPGA
Implications of using the ACP interface in the ETS SoC design
Summary
Questions
Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC
FPGA SoC hardware security features
ARM CPUs and their hardware security paradigm
ARM TrustZone hardware features
Software security aspects and how they integrate the hardware’s available features
Building a secure FPGA-based SoC
Summary
Questions
Chapter 12: Building Complex Software with an Embedded Operating System Flow
Technical requirements
Embedded OS software design flow for Xilinx FPGA-based SoCs
Customizing and generating the BSP and the bootloader for FreeRTOS
Building a user application and running it on the target
Summary
Questions
Chapter 13: Video and Image Processing and DSP Principles in an FPGA and SoCs
DSP techniques using FPGAs
Zynq-7000 SoC FPGA Cortex-A9 processor cluster DSP capabilities
Zynq-7000 SoC FPGA logic resources and DSP improvement
Zynq-7000 SoC FPGA DSP slices
DSP in an SoC and hardware acceleration mechanisms
Accelerating DSP computation using the FPGA logic in FPGA-based SoCs
Video and image processing implementation in FPGA devices and SoCs
Xilinx AXI Video DMA engine
Video processing systems generic architecture
Using an SoC-based FPGA for edge detection in video applications
Using an SoC-based FPGA for machine vision applications
Summary
Questions
Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs
Communication protocol layers
OSI model layers overview
Communication protocols topology
Example communication protocols and mapping to the OSI model
Communication protocol layers mapping onto FPGA-based SoCs
Control systems overview
Control system hardware and software mappings onto FPGA-based SoCs
Summary
Questions
Index
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