This book presents various novel architectures for FPGA-optimized accurate and approximate operators, their detailed accuracy and performance analysis, various techniques to model the behavior of approximate operators, and thorough application-level analysis to evaluate the impact of approximations on the final output quality and performance metrics. As multiplication is one of the most commonly used and computationally expensive operations in various error-resilient applications such as digital signal and image processing and machine learning algorithms, this book particularly focuses on this operation. The book starts by elaborating on the various sources of error resilience and opportunities available for approximations on various layers of the computation stack. It then provides a detailed description of the state-of-the-art approximate computing-related works and highlights their limitations.
Author(s): Salim Ullah, Akash Kumar
Publisher: Springer
Year: 2023
Language: English
Pages: 189
City: Cham
Preface
Acknowledgments
Contents
Acronyms
1 Introduction
1.1 Introduction
1.2 Inherent Error Resilience of Applications
1.3 Approximate Computing Paradigm
1.3.1 Error-Resilient Computing
1.3.2 Stochastic Computing
1.3.3 Approximate Computing
1.3.4 Software Layer Approximation
1.3.5 Architecture Layer Approximation
1.3.6 Circuit Layer Approximation
1.4 Problem Statement
1.4.1 Research Challenge
1.5 Focus of the Book
1.6 Key Contributions and Book Overview
References
2 Preliminaries
2.1 Introduction
2.2 Xilinx FPGA Slice Structure
2.3 Multiplication Algorithms
2.3.1 Baugh-Wooley's Multiplication Algorithm
2.3.2 Booth's Multiplication Algorithm
2.3.3 Sign Extension for Booth's Multiplier
2.4 Statistical Error Metrics
2.5 Design Space Exploration and Optimization Techniques
2.5.1 Genetic Algorithm
2.5.2 Bayesian Optimization
2.6 Artificial Neural Networks
References
3 Accurate Multipliers
3.1 Introduction
3.2 Contributions
3.3 Related Work
3.4 Unsigned Multiplier Architecture
3.5 Motivation for Signed Multipliers
3.6 Baugh-Wooley's Multiplier: Mult-BW
3.7 Booth's Algorithm-Based Signed Multipliers
3.7.1 Booth-Mult Design
3.7.2 Booth-Opt Design
3.7.3 Booth-Par Design
3.7.3.1 Optimizing Critical Path Delay
3.7.3.2 Accumulation of Generated Partial Products
3.8 Constant Multipliers
3.9 Results and Discussion
3.9.1 Experimental Setup and Tool Flow
3.9.2 Performance Comparison of the Proposed Accurate Unsigned Multiplier Acc
3.9.3 Performance Comparison of the Proposed Accurate Signed Multiplier with the State-of-the-Art Accurate Multipliers
3.9.4 Performance Comparison of the Proposed Constant Multiplier with the State-of-the-Art AccurateMultipliers
3.10 Conclusion
References
4 Approximate Multipliers
4.1 Introduction
Contributions
4.2 Related Work
4.3 Unsigned Approximate Multipliers
4.3.1 Approximate 44 Multiplier: Approx-1
4.3.2 Approximate 44 Multiplier: Approx-2
4.3.2.1 Approximate 42 Multiplier
4.3.2.2 Approx-2 Design
4.3.3 Approximate 44 Multiplier: Approx-3
4.4 Designing Higher-Order Approximate Unsigned Multipliers
4.4.1 Accurate Adders for Implementing 88 Approximate Multipliers from 44 Approximate Multipliers
4.4.2 Approximate Adders for Implementing Higher-order Approximate Multipliers
4.5 Approximate Signed Multipliers: Booth-Approx
4.6 Results and Discussion
4.6.1 Experimental Setup and Tool Flow
4.6.2 Evaluation of the Proposed Approximate Unsigned Multipliers
4.6.2.1 Performance Characterization of Designed Multipliers
4.6.2.2 Error Analysis of Proposed Approximate Multipliers
4.6.2.3 Performance Comparison of the Proposed Approximate Multipliers with the State-of-the-Art Multipliers
4.6.2.4 Quality Evaluation of Approximate Multipliers for Application Kernels
4.6.3 Evaluation of the Proposed Approximate SignedMultiplier
4.6.3.1 Error Analysis of Booth-Approx
4.6.3.2 Performance Characterization of Booth-Approx
4.6.3.3 High-Level Application Testing
4.7 Conclusion
References
5 Designing Application-Specific Approximate Operators
5.1 Introduction
5.1.1 Contributions
5.2 Related Work
5.3 Modeling Approximate Arithmetic Operators
5.3.1 Accurate Multiplier Design
5.3.2 Approximation Methodology
5.3.3 Approximate Adders
5.4 DSE for FPGA-Based Approximate Operators Synthesis
5.4.1 DSE Using Bayesian Optimization
5.4.2 MOEA-Based Optimization
5.4.3 Machine Learning Models for DSE
5.5 Results and Discussion
5.5.1 Experimental Setup and Tool Flow
5.5.1.1 ECG Peak Detection
5.5.1.2 Gaussian Smoothing
5.5.1.3 MNIST Digit Recognition
5.5.2 Accuracy-Performance Analysis of ApproximateAdders
5.5.3 Accuracy-Performance Analysis of Approximate Multipliers
5.5.3.1 Multiplier-Level Analysis
5.5.3.2 Application-Level Analysis of Approximate ps: [/EMC pdfmark [/Subtype /Span /ActualText (4 times 4) /StPNE pdfmark [/StBMC pdfmark44ps: [/EMC pdfmark [/StPop pdfmark [/StBMC pdfmark Multipliers
5.5.4 AppAxO_MBO
5.5.5 ML Modeling
5.5.6 DSE Using ML Models
5.5.7 Proposed Approximate Operators
5.5.7.1 Approximate Adders
5.5.7.2 Proposed Approximate Multipliers
5.6 Conclusion
References
6 A Framework for Cross-Layer Approximations
6.1 Introduction
6.2 Related Work
6.3 Contributions
6.4 Error Analysis of Approximate Arithmetic Units
6.4.1 Application-Independent Error Analysis of Approximate Multipliers
6.4.2 Application-Specific Error Analysis
6.5 Accelerator Performance Estimation
6.6 DSE Methodology
6.7 Results and Discussion
6.7.1 Experimental Setup and Tool Flow
6.7.2 Behavioral Analysis
6.7.3 Accelerator Performance Estimation
6.7.4 DSE Performance
6.8 Conclusion
References
7 Conclusions and Future Work
7.1 Conclusions
7.2 Future Works
Index
