Focusing on resource awareness in field-programmable gate array (FPGA) design, Applications of Field-Programmable Gate Arrays in Scientific Research covers the principle of FPGAs and their functionality. It explores a host of applications, ranging from small one-chip laboratory systems to large-scale applications in "big science." The book first describes various FPGA resources, including logic elements, RAM, multipliers, microprocessors, and content-addressable memory. It then presents principles and methods for controlling resources, such as process sequencing, location constraints, and intellectual property cores. The remainder of the book illustrates examples of applications in high-energy physics, space, and radiobiology. Throughout the text, the authors remind designers to pay attention to resources at the planning, design, and implementation stages of an FPGA application, in order to reduce the use of limited silicon resources and thereby reduce system cost. Supplying practical know-how on an array of FPGA application examples, this book provides an accessible overview of the use of FPGAs in data acquisition, signal processing, and transmission. It shows how FPGAs are employed in laboratory applications and how they are flexible, low-cost alternatives to commercial data acquisition systems. Web Resource A supporting website at http://scipp.ucsc.edu/~hartmut/FPGA offers more details on FPGA programming and usage. The site contains design elements of the case studies from the book, including VHDL code, detailed schematics of selected projects, photographs, and screen shots.
Author(s): Hartmut F.-W. Sadrozinski, Jinyuan Wu
Edition: 1
Publisher: Taylor & Francis
Year: 2010
Language: English
Pages: 167
Applications of Field-Programmable Gate Arrays in Scientific Research......Page 1
Applications of Field-Programmable Gate Arrays in Scientific Research......Page 2
Contents......Page 4
Philosophy of this book......Page 8
Additional supporting material......Page 9
Acknowledgments......Page 10
The authors......Page 11
1.3 FPGA costs......Page 12
1.4 FPGA versus ASIC......Page 14
References......Page 15
2.1.1 Logic elements......Page 16
2.1.2 RAM blocks......Page 17
2.2.2 Microprocessors......Page 18
2.3.2 MUX......Page 19
References......Page 20
3.1 Reusing silicon resources by process sequencing......Page 21
3.2 Finding algorithms with less computation......Page 22
3.3 Using dedicated resources......Page 23
3.4.2 Remarks on tri- state buses......Page 24
3.5.2 Preventing useful logic from being synthesized away by the compiler......Page 26
3.6 Guideline on pipeline staging......Page 28
3.7 Using good libraries......Page 29
References......Page 30
4.1.1 LED rhythm control......Page 31
4.1.3 Exponential drop of LED brightness......Page 33
4.2 Simple sequence control with counters......Page 34
4.2.1 Single- layer loops......Page 35
4.2.2 Multilayer loops......Page 37
4.3.1 Essential operations of histogram booking......Page 41
4.3.2 Histograms with fast booking capability......Page 43
4.3.3 Histograms with fast resetting capability......Page 45
4.4 Temperature digitization of TMP03/ 04 devices......Page 47
4.5 Silicon serial number ( DS2401) readout......Page 48
References......Page 51
5.1.1 Antialiasing low- pass filtering......Page 52
5.1.2 Dithering......Page 53
5.2.2 Gain on measurement precision......Page 55
5.2.3 Weighted average......Page 56
5.2.4 Exponentially weighted average......Page 57
5.3 Simple digital filters......Page 59
5.3.1 Sliding sum and sliding average......Page 60
5.3.2 The CIC- 1 and CIC- 2 filters......Page 61
5.4.1 Decimation and the decimation filters......Page 62
5.4.2 The Huffman coding scheme......Page 64
5.4.3 Noise sensitivity of Huffman coding......Page 65
References......Page 66
6.1 TDC in an FPGA based on multiple- phase clocks......Page 67
6.2 TDC in an FPGA based on delay chains......Page 70
6.2.1 Delay chains in an FPGA......Page 71
6.2.2 Automatic calibration......Page 72
6.2.3 The wave union TDC......Page 75
6.3.1 Common start/ stop signals and common burst......Page 77
6.4 ADC implemented with an FPGA......Page 78
6.4.1 The single slope ADC......Page 79
6.4.2 The sigma- delta ADC......Page 81
6.5.1 Pulse width approach......Page 82
6.5.2 Pulse density approach......Page 83
6.6 Zero- suppression and time stamp assignment......Page 85
6.7 Pipeline versus FIFO......Page 86
6.8.1 The C5 pulses and pulse trains......Page 90
6.8.2 The decoder of C5 implemented in an FPGA......Page 91
6.8.3 Supporting front- end circuit via differential pairs......Page 93
6.9 Parasitic event building......Page 94
6.10 Digital phase follower......Page 96
6.11 Multichannel deserialization......Page 100
References......Page 103
7.1 Trigger primitive creation......Page 104
7.2 Unrolling nested- loops, doublet finding......Page 106
7.2.1 Functional block arrays......Page 107
7.2.2 Content- addressable memory ( CAM)......Page 109
7.2.3 Hash sorter......Page 112
7.3 Unrolling nested loops, triplet finding......Page 113
7.3.1 The Hough transform......Page 115
7.4 Track fitter......Page 117
References......Page 121
8.1 Pedestal and RMS......Page 122
8.2 Center of gravity method of pulse time calculation......Page 123
8.3.1 Resource awareness in lookup table implementation......Page 125
8.3.2 An application example......Page 126
8.4 The enclosed loop microsequencer ( ELMS)......Page 129
References......Page 131
9.1.2 SEE effects......Page 132
9.2.2 Space......Page 133
9.3 SEE rates......Page 134
9.4 Special advantages and vulnerability of FPGAs in space......Page 135
9.5.3 Software mitigation: EDAC......Page 136
References......Page 137
10.1 EPTSM system......Page 138
10.2 Time- over- threshold ( TOT): analog ASIC PMFE......Page 140
10.4 FPGA function......Page 142
References......Page 144
Appendix: Acronyms......Page 145
Color insert
......Page 149
