;Advanced FPGA Design Architectur, Implementation and optimization КНИГИ ;АППАРАТУРА Название: Advanced FPGA Design Architectur, Implementation and optimization Автор: Kits S. Год: 2007 Издательство: Wiley-interscienceСтраниц: 354 Размер: 4.9 Mb Формат: pdf Язык: английскийАннотация.This book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized. The topics that will be discussed in this book are essential to designing FPGA's beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience. Uploading.com 0
Author(s): Steve Kilts
Publisher: Wiley-IEEE Press
Year: 2007
Language: English
Commentary: 1181243038
Pages: 352
Advanced FPGA Design......Page 3
Flowchart of Contents......Page 8
Contents......Page 9
Preface......Page 15
Acknowledgments......Page 17
1. Architecting Speed......Page 19
1.1 High Throughput......Page 20
1.2 Low Latency......Page 22
1.3.1 Add Register Layers......Page 24
1.3.2 Parallel Structures......Page 26
1.3.3 Flatten Logic Structures......Page 28
1.3.4 Register Balancing......Page 30
1.3.5 Reorder Paths......Page 32
1.4 Summary of Key Points......Page 34
2. Architecting Area......Page 35
2.1 Rolling Up the Pipeline......Page 36
2.2 Control-Based Logic Reuse......Page 38
2.3 Resource Sharing......Page 41
2.4.1 Resources Without Reset......Page 43
2.4.2 Resources Without Set......Page 44
2.4.3 Resources Without Asynchronous Reset......Page 45
2.4.4 Resetting RAM......Page 47
2.4.5 Utilizing Set/Reset Flip-Flop Pins......Page 49
2.5 Summary of Key Points......Page 52
3. Architecting Power......Page 55
3.1 Clock Control......Page 56
3.1.1 Clock Skew......Page 57
3.1.2 Managing Skew......Page 58
3.2 Input Control......Page 60
3.4 Dual-Edge Triggered Flip-Flops......Page 62
3.5 Modifying Terminations......Page 63
3.6 Summary of Key Points......Page 64
4.1 AES Architectures......Page 65
4.1.2 Zero Stages for Shift Rows......Page 69
4.1.4 One Stage for Add Round Key......Page 70
4.1.5 Compact Architecture......Page 71
4.1.6 Partially Pipelined Architecture......Page 75
4.1.7 Fully Pipelined Architecture......Page 78
4.2 Performance Versus Area......Page 84
4.3 Other Optimizations......Page 85
5.1 Abstract Design Techniques......Page 87
5.2 Graphical State Machines......Page 88
5.3 DSP Design......Page 93
5.4 Software/Hardware Codesign......Page 98
5.5 Summary of Key Points......Page 99
6. Clock Domains......Page 101
6.1 Crossing Clock Domains......Page 102
6.1.1 Metastability......Page 104
6.1.2 Solution 1: Phase Control......Page 106
6.1.3 Solution 2: Double Flopping......Page 107
6.1.4 Solution 3: FIFO Structure......Page 110
6.2 Gated Clocks in ASIC Prototypes......Page 115
6.2.1 Clocks Module......Page 116
6.2.2 Gating Removal......Page 117
6.3 Summary of Key Points......Page 118
7.1 I2S......Page 119
7.1.2 Hardware Architecture......Page 120
7.1.3 Analysis......Page 123
7.2.1 Protocol......Page 125
7.2.2 Hardware Architecture......Page 126
7.2.3 Analysis......Page 132
8.1 Hardware Division......Page 135
8.1.1 Multiply and Shift......Page 136
8.1.2 Iterative Division......Page 137
8.1.3 The Goldschmidt Method......Page 138
8.2 Taylor and Maclaurin Series Expansion......Page 140
8.3 The CORDIC Algorithm......Page 142
8.4 Summary of Key Points......Page 144
9.1 Floating-Point Formats......Page 145
9.2 Pipelined Architecture......Page 146
9.2.1 Verilog Implementation......Page 149
9.2.2 Resources and Performance......Page 155
10. Reset Circuits......Page 157
10.1.1 Problems with Fully Asynchronous Resets......Page 158
10.1.2 Fully Synchronized Resets......Page 160
10.1.3 Asynchronous Assertion, Synchronous Deassertion......Page 162
10.2.1 Nonresetable Flip-Flops......Page 163
10.2.2 Internally Generated Resets......Page 164
10.3 Multiple Clock Domains......Page 166
10.4 Summary of Key Points......Page 167
11. Advanced Simulation......Page 169
11.1.1 Testbench Components......Page 170
11.1.2.1 Main Thread......Page 171
11.1.2.2 Clocks and Resets......Page 172
11.1.2.3 Test Cases......Page 173
11.2.1 MATLAB......Page 175
11.2.2 Bus-Functional Models......Page 176
11.4 Gate-Level Simulations......Page 177
11.5 Toggle Coverage......Page 180
11.6.2 Glitch Rejection......Page 183
11.6.3 Combinatorial Delay Modeling......Page 184
11.7 Summary of Key Points......Page 187
12. Coding for Synthesis......Page 189
12.1.1 Priority Versus Parallel......Page 190
12.1.2 Full Conditions......Page 194
12.1.3 Multiple Control Branches......Page 197
12.2.1 Blocking Versus Nonblocking......Page 198
12.2.2 For-Loops......Page 201
12.2.3 Combinatorial Loops......Page 203
12.2.4 Inferred Latches......Page 205
12.3.1.1 Data Path Versus Control......Page 206
12.3.1.2 Clock and Reset Structures......Page 207
12.3.1.3 Multiple Instantiations......Page 208
12.3.2.1 Definitions......Page 209
12.3.2.2 Parameters......Page 210
12.3.2.3 Parameters in Verilog-2001......Page 212
12.4 Summary of Key Points......Page 213
13.1 SHA-1 Architecture......Page 215
13.2 Implementation Results......Page 222
14. Synthesis Optimization......Page 223
14.1 Speed Versus Area......Page 224
14.2 Resource Sharing......Page 226
14.3 Pipelining, Retiming, and Register Balancing......Page 229
14.3.1 The Effect of Reset on Register Balancing......Page 231
14.3.2 Resynchronization Registers......Page 233
14.4 FSM Compilation......Page 234
14.4.1 Removal of Unreachable States......Page 237
14.5 Black Boxes......Page 238
14.6 Physical Synthesis......Page 241
14.6.1 Forward Annotation Versus Back-Annotation......Page 242
14.6.2 Graph-Based Physical Synthesis......Page 243
14.7 Summary of Key Points......Page 244
15.1 Design Partitioning......Page 247
15.2 Critical-Path Floorplanning......Page 250
15.3 Floorplanning Dangers......Page 251
15.4.2 High Fan-Out......Page 252
15.4.3 Device Structure......Page 253
15.5 Reducing Power Dissipation......Page 256
15.6 Summary of Key Points......Page 258
16.1 Optimal Constraints......Page 259
16.2 Relationship between Placement and Routing......Page 262
16.3 Logic Replication......Page 264
16.4 Optimization across Hierarchy......Page 265
16.5 I/O Registers......Page 266
16.6 Pack Factor......Page 268
16.8 Register Ordering......Page 269
16.9 Placement Seed......Page 270
16.11 Summary of Key Points......Page 272
17.1 SRC Architecture......Page 275
17.2 Synthesis Optimizations......Page 277
17.2.1 Speed Versus Area......Page 278
17.2.2 Pipelining......Page 279
17.3 Floorplan Optimizations......Page 280
17.3.1 Partitioned Floorplan......Page 281
17.3.2 Critical-Path Floorplan: Abstraction 1......Page 282
17.3.3 Critical-Path Floorplan: Abstraction 2......Page 283
18.1 Standard Analysis......Page 287
18.2 Latches......Page 291
18.3 Asynchronous Circuits......Page 294
18.3.1 Combinatorial Feedback......Page 295
18.4 Summary of Key Points......Page 296
19.1.1 Supply Requirements......Page 297
19.2.1 Concept......Page 301
19.2.2 Calculating Values......Page 303
19.2.3 Capacitor Placement......Page 304
19.3 Summary of Key Points......Page 306
Appendix A......Page 307
Appendix B......Page 321
Bibliography......Page 337
Index......Page 339
