Advanced Digital System Design using SoC FPGAs: An Integrated Hardware/Software Approach

Preface
Acknowledgments
Contents
Listings
Acronyms
Part I Introductions
1 Preliminaries
1.1 About This Book
1.1.1 GitHub Repository
1.2 Why Learn About SoC FPGAs?
1.2.1 Further Reading
1.3 Prerequisites
1.3.1 Prior Hardware Knowledge
1.3.2 Prior Software Knowledge
1.4 Hardware Needed
1.4.1 Laptop
1.4.2 DE10-Nano FPGA Board
1.4.3 Audio Board
1.4.4 Miscellaneous Hardware
1.5 Software Needed
1.6 The Development Landscape
References
2 Introduction to System-on-Chip Field Programmable Gate Arrays
2.1 The Digital Revolution
2.2 Basic FPGA Architecture
2.2.1 External I/O
2.2.2 Logic Elements
2.2.3 Memory
2.2.4 DSP Blocks
2.3 SoC FPGA Architecture
References
3 Introduction to the SoC FPGA Boot Process
3.1 Cyclone V SoC FPGA Boot Process
3.1.1 Boot Step 1: Power-Up or Reset
3.1.2 Boot Step 2: Boot ROM
3.1.3 Boot Step 3: Preloader
3.1.4 Boot Step 4: U-boot
3.1.5 Boot Step 5: Linux
3.1.6 Boot Step 6: Application
References
4 Introduction to the DE10-Nano Board
4.1 DE10-Nano Board
4.1.1 Determining DE10-Nano Board Revision
4.1.2 DE10-Nano Information
4.1.3 DE10-Nano Cyclone V SoC FPGA
4.1.4 DE10-Nano Configuration Mode Switch Setting
References
5 Introduction to the Audio Mini Board
5.1 Top Level Block Diagram
5.2 Analog Audio Input
5.3 AD1939 Audio Codec
5.3.1 AD1939 Serial Data Port
5.3.1.1 Data to the FPGA from the AD1939 ADC
5.3.1.2 Data to the AD1939 DAC from the FPGA
5.3.1.3 AD1939 FPGA Data Interfacing
5.3.2 AD1939 SPI Control Port
5.3.2.1 AD1939 Register Settings
5.4 Headphone Analog Audio Output
5.4.1 TPA6130A2 I2C Interface
5.4.1.1 TPA6130A2 Register Settings
5.5 DE10-Nano FPGA Connections
References
6 Introduction to Intel Quartus Prime
6.1 Intel Quartus Prime Lite Edition
6.1.1 Installing Windows for Subsystem for Linux (WSL)
6.1.2 Download and Install Intel's Quartus Prime Lite
6.1.3 Quartus File Types
6.1.4 Converting Programming Files
6.1.5 Timing
6.1.6 Learning Quartus
6.2 Platform Designer
6.2.1 Creating an Avalon Memory-Mapped Interface
6.2.1.1 Creating Component Registers
6.2.2 Creating a Custom Platform Designer Component
6.2.3 Creating an Avalon Streaming Interface
6.3 System Console
6.3.1 The General Flow for Using System Console
6.3.2 Modifying the Design in Platform Designer
6.3.3 Using System Console
6.3.4 Summary of System Console Commands
6.4 Creating IP in Quartus
6.4.1 Creating a ROM IP Component
6.4.1.1 Creating the ROM Memory Initialization File
6.4.1.2 Creating the ROM IP
References
7 Introduction to Memory Addressing
7.1 The View of Memory from the ARM CPUs and Platform Designer
7.1.1 Memory Addressing for Registers on the HPS Lightweight Bus
7.2 The View of Memory from System Console
Reference
8 Introduction to Verification
8.1 Design Assumptions
8.1.1 Synchronous Designs
8.1.2 Hierarchical Designs
8.1.3 VHDL Code Formatting
8.2 Verification
8.2.1 Why Verify?
8.2.2 Verification Process
8.3 Verification Example 1: File I/O
8.3.1 VHDL File to Verify: my_component1.vhd
8.3.2 VHDL Testbench File: my_component1_tb.vhd
8.3.3 Creating Test Vectors with Matlab Script my_test_vectors1.m
8.3.4 Computing the Results with Matlab Function my_component1.m
8.3.5 Performing Verification with the Matlab Script my_verification1.m
8.3.6 Running the Example 1 Verification
8.4 Verification Example 2: Using a Quartus ROM IP Component
8.4.1 VHDL File to Verify: my_component2.vhd
8.4.2 VHDL Testbench File: my_component2_tb.vhd
8.4.3 Creating Test Vectors with Matlab Script my_test_vectors2.m
8.4.4 Computing the Results with Matlab Function my_component2.m
8.4.5 Performing Verification with the Matlab Script my_verification2.m
8.4.6 Running the Example 2 Verification
8.5 Homework Problems
9 Introduction to Linux
9.1 The Linux View of Memory
9.2 Cross Compiling the Linux Kernel
9.2.1 Packages Needed
9.2.2 Get the Linux Source Repository and Select the Git Branch
9.2.3 Configuring the Kernel
9.2.4 Cross Compiling the Kernel
9.3 Kernel Modules
9.3.1 Loadable Kernel Modules
9.3.2 Cross Compiling the Kernel Module
9.3.3 Inserting the Kernel Module into the Linux Kernel
9.4 Device Trees
9.4.1 Device Tree Basics
9.4.2 Device Tree Hierarchy
9.4.3 Creating a Device Tree for Our DE10-Nano System
9.5 Platform Device Driver
9.6 Steps for Creating a Platform Device Driver for Your Custom Component in Platform Designer
9.6.1 Testing the Platform Device Driver
9.7 List of Linux Commands
References
10 Introduction to Digital Signal Processing
10.1 Sampling
10.2 Fourier Series
10.3 Geometric Interpretation of the Fourier Transform
10.4 The Fast Fourier Transform (FFT)
10.4.1 The Discrete Time Continuous Frequency Fourier Transform
10.4.2 The Discrete Fourier Transform
10.4.3 FFT
10.5 Practical Considerations When Using the FFT
10.5.1 Windowing
10.5.2 Window Length
10.5.3 Window Edge Effects
10.5.4 Window Trade-Offs
References
Part II SoC FPGA System Development
11 Development Environment Setup
11.1 Software Setup
11.1.1 Setting up a PuTTY Terminal Window in Windows to Communicate with Linux on the DE10-Nano Board
11.1.1.1 Finding the COM Port Assigned by Windows
11.1.1.2 PuTTY Setup
11.1.2 VirtualBox Ubuntu Virtual Machine Setup
11.1.2.1 Overview
11.1.2.2 Enable Virtualization in Your PC's BIOS
11.1.2.3 Download VirtualBox
11.1.2.4 Download Ubuntu
11.1.2.5 VirtualBox Installation
11.1.2.6 Setting up Ubuntu in VirtualBox
11.1.2.7 Install and Configure Needed Software in the Ubuntu VM
11.1.2.8 Configure VirtualBox
11.1.2.9 Give Yourself Permission to Access Shared Folders in Ubuntu VM
11.1.2.10 Install More Software in Ubuntu VM
11.1.2.11 Testing the Ubuntu VM by Compiling ``Hello World''
11.1.3 Developer's Boot Mode Setup
11.1.3.1 Install the USB Ethernet Adapter
11.1.3.2 Network Configuration in the VirtualBox Manager
11.1.3.3 Network Setup in the Ubuntu VM
11.1.3.4 TFTP Server Setup in the Ubuntu VM
11.1.3.5 NFS Server Setup in the Ubuntu VM
11.1.3.6 Reimaging the microSD Card with the Developer's Image
11.1.3.7 DE10-Nano Board Switch Settings
11.1.3.8 Setting U-boot Variables on the DE10-Nano Board to Boot via NFS/TFTP
11.1.3.9 Setting Up the Audio Mini Passthrough Example
11.1.3.10 Running the Audio Mini Passthrough Example
11.1.4 Cross Compiling ``Hello World''
11.1.4.1 Configure and Set up the Linaro GCC ARM Tools in Ubuntu VM
11.1.4.2 Manual Cross Compilation of Hello World
11.1.4.3 Makefile Cross Compilation of Hello World
11.2 List of U-boot Commands
References
12 Creating a LED Pattern Generator System
12.1 LED_Patterns Component
12.1.1 LED_Patterns Entity
12.1.2 Functional Requirements for LED_Patterns
12.1.2.1 State Machine
12.1.2.2 Conditioning the Push-Button Signal
12.1.3 Suggested Architecture
12.2 Homework Problems
Part III SoC FPGA System Examples
Example 1 Audio FPGA Passthrough
1.1 Audio Passthrough System Overview
1.2 Audio Data Streaming
1.2.1 I2S to Avalon Streaming Data Conversion
1.2.1.1 Serial to Parallel Conversion
1.2.1.2 Avalon Streaming Output Interface
1.2.1.3 Avalon Streaming Input Interface
1.2.1.4 Parallel to Serial Conversion
1.2.1.5 Serial Data Multiplexing
1.2.1.6 Clocking
1.3 Quartus Passthrough Project
1.4 Platform Designer
1.4.1 Creating the AD1939 Platform Designer Component
1.4.2 Creating a Platform Designer Subsystem for the AD1939
1.4.3 Creating the Platform Designer Passthrough System
1.4.3.1 Adding the AD1939 Subsystem
1.4.3.2 Adding the SPI and I2C Interfaces to the hps Component
1.4.4 Generating the Platform Designer System
1.4.4.1 Platform Designer soc_system Entity and Port Map
1.4.4.2 Hooking Up the soc_system_passthrough System in the Top Level
1.5 Linux Device Drivers
1.5.1 Linux SPI Device Driver for the AD1939 Audio Codec
1.5.2 Linux I2C Device Driver for the TPA6130A2 Headphone Amplifier
1.5.3 Linux Device Tree
1.5.4 Loading the Linux Device Drivers on Boot
Example 2 Feedforward Comb Filter System
2.1 Overview
2.1.1 Feedback Comb Filter
2.1.2 Comb Filter Uses
2.2 Simulink Model
2.2.1 Overview of the Simulink Model Files
2.2.2 Simulink Common Files
2.2.3 Model Specific Files
2.3 Creating the Simulink Model
2.4 VHDL Code Generation Using Simulink's HDL Coder
2.4.1 Common Model Errors
2.4.2 Simulink Setup for HDL Coder
2.4.3 HDL Workflow Advisor
2.4.3.1 Clocking
2.4.3.2 Generating VHDL Code
2.4.3.3 VHDL Files
2.5 HPS Integration Using Platform Designer
2.5.1 Hardware Integration Steps
2.5.2 Quartus Project Setup
2.5.3 Creating the Platform Designer Component
2.5.4 Importing combFilterProcessor into Platform Designer
2.5.5 Testing the combFilterProcessor Using System Console
2.5.6 Quartus Project Cleanup
2.6 Linux Device Driver
References
Example 3 FFT Analysis Synthesis System
3.1 Overview
3.1.1 Frequency Domain Processing
3.2 Simulink Model Files
3.3 Creating the Simulink Model
3.3.1 Analysis
3.3.2 Simulink Logic Analyzer
3.3.3 Frequency Domain Processing
3.3.4 Synthesis
3.3.5 Verification
3.3.6 System Latency
3.4 VHDL Code Generation Using Simulink's HDL Coder
3.5 HPS Integration Using Platform Designer
3.5.1 Hardware Integration Steps
3.5.2 Testing the fftAnalysisSynthesisProcessor Using System Console
3.6 Linux Device Driver
Reference
Part IV Labs
1 Setting Up the Ubuntu Virtual Machine
1.1 Items Needed
1.2 Lab Steps
1.3 Demonstration
1.4 Deliverables
1.4 Sign-off Sheet
2 Hardware Hello World
2.1 Items Needed
2.2 Lab Steps
2.3 Demonstration
2.4 Deliverables
2.4 Sign-off Sheet
3 Developer's Setup
3.1 Items Needed
3.2 Lab Steps
3.3 Demonstration
3.4 Deliverables
3.4 Sign-off Sheet
3.5 Common Problems and Solutions
3.5.1 Problem: Serial Connection to DE10-Nano in PuTTY (Or Similar) is Not Working
3.5.2 Problem: DE10-Nano Cannot Connect to the Virtual Machine
3.5.3 Problem: Virtual Machine Does Not Boot
3.5.4 Problem: DE10-Nano Cannot Download Files from TFTP Server
3.5.5 Problem: No Internet Connection in Virtual Machine
3.5.6 Problem: DE10-Nano Fails to Mount the Rootfs Over NFS, Resulting in a Kernel Panic
3.5.7 Problem: You Tried to Copy a File to a Directory, but the Directory Shows up as a File
3.5.8 Problem: Copying a File Results in a Permission/Access Denied Error
3.5.9 Problem: Running a Makefile or Similar Results in a Permission/Access Denied Error
3.5.10 Problem: I Get an ``altera_load: Failed with Error Code -4'' When Booting Up My Board
4 LED Patterns
4.1 Items Needed
4.2 Lab Steps
4.3 Demonstration
4.4 Deliverables
4.4 Sign-off Sheet
4.5 Common Problems and Solutions
4.5.1 Problem: Hardware State Machine Works When Reset Is Held Down
4.5.2 Problem: Hardware State Machine Only Displays the Switch State, Not the Patterns
4.5.3 Problem: Nothing Works
4.5.4 Problem: I Cannot Program the Board
5 Signal Tap
5.1 Items Needed
5.2 Lab Steps
5.3 Demonstration
5.4 Deliverables
5.4 Sign-off Sheet
6 Creating a Custom Hardware Component in Platform Designer
6.1 Items Needed
6.2 Lab Steps
6.3 Demonstration
6.4 Deliverables
6.4 Sign-Off Sheet
6.5 Common Problems and Solutions
6.5.1 Problem: Error Generating System with Platform Designer or Compiling the System in Quartus
7 Verifying Your Custom Component Using System Console and /dev/mem
7.1 Items Needed
7.2 Lab Steps
7.3 Demonstration
7.4 Deliverables
7.4 Sign-Off Sheet
7.5 Common Problems and Solutions
7.5.1 Problem: Hardware State Machine Keeps Running the LEDs After Setting HPS_LED_control to a 1 (Software Control Mode)
7.5.2 Problem: The Values Written to Registers Do Not Show Up
7.5.3 No JTAG Masters Show Up in System Console
7.5.4 Downloading the Bitstream When the Programmer Fails
8 Creating LED Patterns with a C Program Using /dev/mem in Linux
8.1 C Program Requirements
8.2 Items Needed
8.3 Lab Steps
8.4 Demonstration
8.5 Deliverables
8.5 Sign-off Sheet
9 Linux Kernel Module Hello World
9.1 Items Needed
9.2 Lab Steps
9.3 Demonstration
9.4 Deliverables
9.4 Sign-Off Sheet
10 Modifying the Linux Device Tree
10.1 Items Needed
10.2 Lab Steps
10.3 Demonstration
10.4 Deliverables
10.4 Sign-off Sheet
11 Creating a Platform Device Driver for the HPS_LED_Patterns Component
11.1 Items Needed
11.2 Lab Steps
11.3 Demonstration
11.4 Deliverables
11.4 Sign-off Sheet
12 Implementing the Passthrough Project
12.1 Items Needed
12.2 Lab Steps
12.3 Demonstration
12.4 Deliverables
12.4 Sign-off Sheet
13 Implementing the Comb Filter Project
13.1 Items Needed
13.2 Lab Steps
13.3 Demonstration
13.4 Deliverables
13.4 Sign-off Sheet
14 Implementing the FFT Analysis Synthesis Project
14.1 Items Needed
14.2 Lab Steps
14.3 Demonstration
14.4 Deliverables
14.4 Sign-off Sheet
15 Creating Your Sound Effect in Simulink
15.1 Items Needed
15.2 Lab Steps
15.3 Demonstration
15.4 Deliverables
15.4 Sign-off Sheet
16 Implementing Your Sound Effect in the FPGA Fabric
16.1 Items Needed
16.2 Lab Steps
16.3 Demonstration
16.4 Deliverables
16.4 Sign-off Sheet
17 Writing a Linux Device Driver to Control Your Sound Effect Processor
17.1 Items Needed
17.2 Lab Steps
17.3 Demonstration
17.4 Deliverables
17.4 Sign-off Sheet
Index