Author(s): ACM-SIGDA
Publisher: ACM-SIGDA
Year: 1993
Language: English
Commentary: Complete
Pages: 256
WELCOME......Page 3
Final Program and Table of Contents......Page 4
Two-Stage Simulated Annealing......Page 6
Fast, High-Quality Placement for Large Circuits......Page 16
A New Optimization Driven Clustering Algorithm forLarge Circuits (Extended Abstract)......Page 18
A Constructive Area Optimisation Algorithm forGeneral Floorlan Structure......Page 25
High Performance Multichip Interconnection Design......Page 37
Toward Optimal Routing Trees......Page 49
The Net Matching Problem in High PerformanceMicroelectronics Design......Page 57
A Multilayer Assignment Algorithm for Interference Minimization......Page 68
XY and Z-Direction Coupled Noise Minimizationin Multichip Module Layout Design......Page 73
A Midway Router for General Architecture Designs......Page 85
Optimal Channel Density Minimization byOver-the-Cell Routing......Page 86
A Space-efficient Short-finding Algorithm......Page 98
FLEXIBLE MACROCELL LAYOUT GENERATOR......Page 110
A New Algorithm for Two Dimensional Multiple Folding......Page 122
Physical Modeling of Datapath Librariesfor Design Automation Applications......Page 134
Design of High Throughput Data Path Components......Page 146
Generic RT Component Sets and Rapid Technology Projectionfor High-Level Design Applications......Page 157
Reduction of Routing Areain High-Level Synthesis......Page 168
Incorporating Interconnection Delays in VHDL BehavioralSynthesis......Page 180
Finding Uni-Directional Cuts Based on Physical Partitioning andLogic Restructuring......Page 192
Heuristic Methods for Communication-Based Logic Partitioning......Page 204
FPGA MCM Partitioning and Placement......Page 216
On the Segmentation Design and Routability Analysis Problems forRow-based FPGAs......Page 218
A Detailed Routing Algorithm for Allocating WireSegments in Field-Programmable Gate Arrays......Page 220
Performance-Driven Placement with Cell Sizing forStandard-Cell Integrated Circuits......Page 232
Optimal Clustering for Delay Minimization......Page 244
Index of Authors......Page 256
