This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.
Author(s): Vaibhav Gogte, Aasheesh Kolli, Thomas F. Wenisch
Series: Synthesis Lectures on Computer Architecture
Publisher: Springer
Year: 2022
Language: English
Pages: 114
City: Cham
Cover
Copyright Page
Title Page
Contents
Preface
Acknowledgments
Persistent Memories
Introduction
Persistent Memory Technologies
Intel Optane DC Persistent Memory
Performance of Optane DC Persistent Memory
Modeling Persistent Memory Systems
SYSTEM CONFIGURATIONS
Traditional Storage Systems
Persistent Memory System
Persistent Memory Support in Existing File Systems
Persistent Memory File Systems
Direct Access to Persistent Memories
Data Persistence
Ensuring Data Durability
Persistence at CPU Caches
Persistence at PM Controller
Persistence at Persistent Memory Device
ARMv8.2 ISA Extensions
Ordering Memory Operations to PM
Why is Ordering Required?
Sources of PM Operation Reordering
Applying Correct Memory Order to PM
Memory Persistency Models
Persistency Models
Recovery Observer
Strict Persistency
Buffered Strict Persistency Model
Formalizing the Strict Persistency Model
Persist Ordering Examples
Hardware Implementations of Strict Persistency
Naive Implementation
Bulk Persistence
Delegated Persistence
Drawbacks of Strict Persistency
Epoch Persistency Model
Strong Persist Atomicity
Buffered Epoch Persistency Model
Formalizing the Epoch Persistency Model
Persist Ordering Examples
Hardware Implementations of Epoch Persistency
Naive Implementation
Buffered Epoch Persistency in Hardware
Offline Conflict Resolution
Separate Ordering and Durability Barriers
Drawbacks of Epoch Persistency
Strand Persistency Model
Strong Persist Atomicity
Formalizing the Strand Persistency Model
Persist Ordering Examples
Hardware Implementations of Strand Persistency
Hardware Mechanisms for Atomic Durability
Failure Atomicity
Write-Ahead Logging
Log Structuring
Shadow Paging
Failure-Atomic Mechanisms
Hardware Undo Logging
Naive Implementation
Optimized Undo Logging
Software-Assisted Hardware Logging
Hardware Redo Logging
Optimized Redo Logging
Durable Hardware Transactions
Hardware Checkpointing Mechanisms
Coarse-Grained Checkpointing
Checkpointing on Power Failure
Programming Persistent Memory Systems
File Systems
Ext4 DAX
NOVA File System
Splitfs
Strata
Programming PM Systems
Transactional Failure Atomicity
Intel’s PMDK libraries
Deferred Commit Transactions
Failure Atomicity for Outer-Critical Section
Failure Atomicity for Synchronization Free Region
Testing PM Applications
Conclusion
Bibliography
Authors’ Biographies
