This document describes planned extensions to the Intel 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware.
Retrieved from https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf on 2017 May 09.
Author(s): coll.
Series: Document Number: 335252-001
Edition: Revision 1.0
Publisher: Intel Corporation
Year: 2016
Language: English
Pages: 26
1
2
3
4
5
Figures
Introduction .............................................................................................................. 3
1.1
Existing Paging in IA-32e Mode ............................................................................. 3
1.2
Linear-Address Width and VMX Transitions ............................................................. 5
1.3
Existing Extended Page Tables (EPT)...................................................................... 6
Expanding2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Linear Addresses: 5-Level Paging ............................................................. 7
5-Level Paging: Introduction ................................................................................. 7
Enumeration and Enabling .................................................................................... 7
2.2.1 Enumeration by CPUID.............................................................................. 7
2.2.2 Enabling by Software ................................................................................ 8
Linear-Address Generation and Canonicality............................................................ 8
5-Level Paging: Linear-Address Translation............................................................. 9
Linear-Address Registers and Canonicality ............................................................ 10
2.5.1 Canonicality Checking on RIP Loads .......................................................... 11
2.5.2 Canonicality Checking on Other Loads ....................................................... 12
Interactions with TLB-Invalidation Instructions ...................................................... 13
Interactions with Intel® MPX .............................................................................. 14
Interactions with Intel® SGX .............................................................................. 15
Linear-Address Expansion and VMX Transitions....................................................... 17
3.1
Linear-Address Expansion and VM Entries ............................................................. 17
3.2
Linear-Address Expansion and VM Exits................................................................ 17
5-Level EPT ............................................................................................................. 19
4.1
4-Level EPT: Guest-Physical-Address Limit............................................................ 19
4.2
5-Level EPT: Enumeration and Enabling ............................................................... 19
4.2.1 Enumeration.......................................................................................... 19
4.2.2 Enabling by Software .............................................................................. 20
4.3
5-Level EPT: Guest-Physical-Address Translation ................................................... 20
4.4
5-Level EPT and EPTP Switching .......................................................................... 21
Intel® Virtualization Technology for Directed I/O ................................................... 23
1-1
2-1
Linear-Address Translation Using IA-32e Paging ...................................................... 4
Linear-Address Translation Using 5-Level Paging ................................................... 11
Tables
2-1
Format of a PML5 Entry (PML5E) that References a PML4 Table ................................. 9
4-1
Format of an EPT PML5 Entry (EPT PML5E) ........................................................... 20
