USB 3.0 Technology: Comprehensive Guide to SuperSpeed USB

Book Cover
Table of Contents
About This Book
Scope
The MindShare Architecture Series
Cautionary Note
The Standard Is the Final Word
Documentation Conventions
Hexadecimal Notation
Binary Notation
Decimal Notation
Bits Versus Bytes Notation
Bit Fields
Other Terminology and Abbreviations
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1 Motivation for USB 3.0
Introduction
USB 3.0 Host Controllers
Performance
USB Bandwidth Comparison
Streaming Video and Audio
Mass Storage
Improved Protocols
End-to-End Protocols
Token/Data/Handshake Shortcomings and Improvements
Token/Data/Handshake is Inefficient.
Broadcast Bus Increases Power Consumption
Polled Flow Control.
Error Handling and Reporting
Data Bursting
Bulk Streaming
Port-to-Port Protocols
Link Flow Control
Link Error Detection and Recovery
Power Management
SuperSpeed Bus Power Management
Broadcast Versus Unicast Bus
Link Power Management
Function Power Management
System Power Improvements
2 USB 2.0 Background
Motivations for USB
USB Topologies
USB 2.0 Companion Controllers
Host Controller Registers
USB Hubs
Root Hubs
External Hubs
Hub Depth Limits
Broadcast Transactions
Device Architecture
Endpoints and Buffers
Control Endpoints
Standard Requests
Optional Endpoints
USB 2.0 Packets and Protocol
Token-Data-HandShake Packet Protocol
IN Transactions
OUT Transactions
Low-Speed Transaction Variation
Control Transfer Stages
Three-Stage Transfers
Two-Stage Transfers
Maximum Payload Sizes
HS Ping Protocol - For OUT Transactions
HS Split Transaction Protocol
Transaction Generation and Scheduling
Transaction Generation
Transaction Scheduling
Device Power
3 USB 3.0 Overview
USB 3.0 Topology and Compatibility
USB 3.0 Host Controller
Topology
USB 2.0/3.0 Compatibility
Receptacle and Plug Compatibility
SuperSpeed Device Compatibility
Software Compatibility
The SuperSpeed Physical Layer Environment
USB 3.0 Composite Cable
SS Link Models
Shared Bus Power
USB 3.0 Compliant Cable Assemblies
General
USB 3.0 Power-B Connections
SuperSpeed Layered Interface and Protocols
Hub Interface Layers
Layers - Hub Forwarding Packets
Layers - Hub as Target
Layers - Hub Downstream Port (Thin Protocol Layer)
Three Protocol Layers
End-to-End Protocol (Protocol Layer)
USB 2.0 vs SS IN Transaction Comparison
USB 2.0 vs SS OUT Transaction Comparison
Port-to-Port Protocol (Link Layer)
Chip-to-Chip Protocol (Physical Layer)
Configuration and Descriptors
Power Management
Link Power Management
Function Power Management
4 Introduction to End-to-End Protocol
The Protocols
The Protocol Packet Types
The Token Lives On
Data Bursting
Bulk Endpoint Streaming
Endpoint Characteristics for SuperSpeed
Port-to-Port Protocol Influence
Does SuperSpeed Support Parallel Operations?
5 End-to-End Packets
Three Categories of End-To-End Packets
Transaction Packets (TPs)
ACK Header
Downstream Moving ACK
Upstream Moving ACK
NRDY Header
ERDY Header
STATUS Header
STALL Header
Notification Headers
Function Wake Header
Latency Tolerance Message Header
Bus Interval Adjustment Message Header
PING and PING RESPONSE Header
Data Packet
DATA Packet Moving Downstream
DATA Packet Moving Upstream
Isochronous Timestamp Packet (ITP)
6 Control Protocol
Introduction to SuperSpeed Control Transfers
Control Transfer Structures and Examples
Two-Stage Control Transfer Structure
Three-Stage Control Transfer Structure
Control IN Example - Single Data Packet
Control IN Example - Two Data Packets
Control OUT Example - Two DATA Packets
Control Transfer Packet Content
The Setup Transaction
The DATA Header Packet
Data Packet Payload - Setup Data
Setup Response - ACK
DATA Stage
Status Stage
General
Control Transfer with STALL
Two Stage Control Transfer Example
Set Address Request
Setup Stage - Set Address
Status Stage - Set Address
Protocol Details for Set Address Request
Three Stage IN Control Transfer Examples
The Get Device Descriptor Request Example
Setup Transaction - Get Device Descriptor
Data and Status Stages - Get Device Descriptor
Protocol Details - Get Device Descriptor Request
Control Transfer - Variable-Length Data Example 1
Control Transfer - Variable-Length Data Example 2
7 Bulk Protocol
Introduction to Bulk Transfers
Bulk End-to-End Protocol
Bulk IN SuperSpeed Transaction Protocol
IN Data Bursting
Single DATA Packet Burst Example
Burst IN Example with Four DATA Packets
Burst IN Example with Long Burst
End-to-End Flow Control - Bulk IN Transfers
NRDY Flow Control at Start of IN Transfer
IN Burst Flow Control Using EOB
IN Burst Flow Control Using NRDY
Short packets
Data IN Transfer Errors and Retry
Bulk OUT SuperSpeed Transaction Protocol
OUT Data Bursting
Single DATA OUT Burst Example
Burst OUT Example with Four DATA Packets
Burst OUT Example with Long Burst
End-to-End Flow Control - Bulk OUT Transfers
NRDY Flow Control at Start of OUT Transfer
OUT Burst Flow Control Using NumP=0
DATA OUT Transfer Errors
Timeout conditions and values
Standard Bulk Vs. Bulk Streaming Endpoints
Streaming And Endpoint Buffers
Standard Bulk Endpoint Buffer
Bulk Streaming Endpoint Buffers
Stream ID (SID), A Bit More
Priming the Bulk Streaming Endpoints
Reporting Bulk Endpoint Streaming Capability
Standard And Bulk Streaming Examples
Standard Bulk Endpoints & SCSI BOT Drive
Standard Device Endpoints
Host Memory Buffers
Host Controller (HC)
BOT Disk DMA Read Operation
Bulk Streaming Endpoints & UAS Drives
UAS Device Endpoints
Host Memory Buffers
Host Controller (HC)
Example UAS and UASP Commands
The Non-Data UAS Command
Non Data UASP Command
Read DMA UAS Command
Read DMA UASP Command
Write DMA UAS Command
Write DMA UASP Command
8 Interrupt Protocol
Introduction to Interrupt Transfers
Interrupt IN SuperSpeed Transaction Protocol
Single Interrupt Transaction
Interrupt Burst Transactions (two DATA packets)
Interrupt IN - Errors and Retries
Interrupt OUT SuperSpeed Transaction Protocol
Interrupt OUT Data Bursting
End-to-End Flow Control - Interrupt OUT Transfers
9 Isochronous Protocol
Introduction to Isochronous Transfers
Bus Intervals and Isochronous Service Intervals
Flexibility of Scheduling
Isochronous Timestamp Packet Delivery
General
The Timestamp Packet
Delta Value
Delayed Bit
Changing the Time Base
Requirements for Changing the Time Base
Bus Interval Adjustment Message
Ping and Ping Response
Ping Related Timing Parameters
Maximum Exit Latency (MEL)
tPingTimeout
Ping and Ping Response Header Format
Isochronous End-to-End Protocol
General Isochronous IN Protocol Rules
Isochronous IN Protocol
Isochronous IN with Burst of Two
Isochronous IN Burst of Two with Zero Payload
Isochronous IN Burst Size of 16
Isochronous OUT Transactions
Isochronous OUT with Burst Size of 16
Isochronous OUT Burst with Four Service Intervals
Service Interval N
Service interval N+1
Service Interval N+2
Service Interval N+3
Smart Isochronous Transaction Scheduling
Smart Isochronous IN Transaction Example
Smart Isochronous IN Transactions with No Ping
Smart Isochronous OUT Transactions
10 USB 3.0 Hubs
Introduction to SS Hubs
Hub Attachment
Packet Forwarding
Packet Forwarding and the Layers
Packet Routing Across Hub - Link-to-Link
Packet Routing to Hub Controller
Packet Routing to Hub Controller with LMP
Unicast Routing
Packet Forwarding and Buffer Requirements
Header Buffers - Store and Forward Model
Data Payload Buffers - The Repeater Model
Transaction Deferral
Hub Error Detection and Handling
Hub Link Power Management Responsibilities
Cable Power and Distribution
Reset Propagation
11 Introduction to Port-To-Port Protocol
Port-To-Port Protocol And The Link Layer
The Big Picture Revisited
Port-To-Port Protocol: Header Processing
General
Header Fields, Two Groups
Link Layer Header Processing Elements
Tx HP Processing
Tx HP Buffers
Tx Data CRC-32 Generation
Rx HP Checks
Rx HP Buffers
Rx Data CRC-32 Checking
Link Management Elements
LTSSM Functional Block
Tx, Rx Link Commands
Link Command Groups
Packet Acknowledgement Link Commands
Flow Control Link Commands
Power Management Link Commands
Link Up/Link Down Link Commands
HP Acknowledgement
HP Flow Control
Ordered Sets
Ordered Set Data (D) and Control (K) Symbols
Four Ordered Set Functional Groups
Framing Ordered Sets (Delimiters)
Header Packet Framing
Data Packet Framing (Valid Data Payload)
Data Packet Framing (Nullified Data Payload)
Link Command Framing
Link Training & Retraining Ordered Sets
TSEQ Ordered Set
TS1 Ordered Set
TS2 Ordered Set
Clock Compensation Ordered Set (Skip Ordered Set)
Loopback Bit Error Rate Test (BERT) Ordered Sets
General
BRST Ordered Set
BERC Ordered Set
BCNT Ordered Set
12 LTSSM And the SuperSpeed Link States
Twelve High Level LTSSM States
Why Is The LTSSM Needed?
LTSSM Link Training And Retraining
Background: USB 2.0 Doesn’t Require Training
LTSSM Coordinates SuperSpeed Link Training
LTSSM And Link-Level Error Handling
Background: USB 2.0 Approach to Bus Errors
USB 3.0 SuperSpeed Approach To Link Errors
When Does The LTSSM Become Involved?
LTSSM And SuperSpeed Link Power Management
Background: USB 2.0 Power Management
USB 3.0 SuperSpeed Power Management Enhancements
The LTSSM Role In SuperSpeed Link Power Management
LTSSM And SuperSpeed Link Testing
Background: USB 2.0 Testing
USB 3.0 SuperSpeed Link Testing Features
LTSSM State Transitions
General
What Is A Directed LTSSM Transition?
Handshake Signaling Locks LTSSMs
LTSSM Handshake Takes Several Forms
LFPS Signaling Events Used In LTSSM Handshake
Ordered Sets Used In LTSSM Handshake
Link Commands Used In LTSSM Handshake
LTSSM Time-outs
General
Timer Characteristics
LTSSM Reference Section Note
Summary Of LTSSM Operational States
U0
General Description
Requirements In The U0 State
Exit Rules For The U0 State
U1
General Description
Requirements In The U1 State
Exit Rules For The U1 State
U2
General Description
Requirements In The U2 State
Exit Rules For The U2 State
U3 (Suspend)
General Description
Requirements In The U3 State
Exit Rules For The U3 State
Summary Of LTSSM Link Initialization &Training States
Rx.Detect
General Description
Requirements In The Rx.Detect.Reset Substate
Exit Rules For The Rx.Detect.Reset Substate
Requirements In The Rx.Detect.Active Substate
Exit Rules For The Rx.Detect.Active Substate
Requirements In The Rx.Detect.Quiet Substate
Exit Rules For The Rx.Detect.Quiet Substate
Polling
General Description
Requirements In The Polling.LFPS Substate
Exit Rules For The Polling.LFPS Substate
Requirements In The Polling.RxEQ Substate
Exit Rules For The Polling.RxEQ Substate
Requirements In The Polling.Active Substate
Exit Rules For The Polling.Active Substate
Requirements In The Polling.Configuration Substate
Exit Rules For The Polling.Configuration Substate
Requirements In The Polling.Idle Substate
Exit Rules For The Polling.Idle Substate
Recovery
General Description
Requirements In Recovery.Active
Exit Rules For Recovery.Active
Requirements In Recovery.Configuration
Exit Rules For Recovery.Configuration
Requirements In Recovery.Idle
Exit Rules For Recovery.Idle
Hot Reset
General Description
Requirements In Hot Reset.Active
Exit Rules For Hot Reset.Active
Requirements In Hot Reset.Exit
Exit Rules For Hot Reset.Exit
Summary Of LTSSM Testing States
Compliance Mode
General Description
Requirements In Compliance Mode
Exit Rules For Compliance Mode
Loopback
General Description
Requirements In Loopback.Active
Exit Rules For Loopback.Active
Requirements In Loopback.Exit
Exit Rules For Loopback.Exit
Summary Of Other LTSSM States
SS.Inactive State
General Description
Basic SS.Inactive Requirements
Requirements In SS.Inactive.Quiet Substate
Exit Rules For SS.Inactive.Quiet Substate
Requirements In SS.Inactive.Disconnect.Detect
Exit Rules For SS.Inactive.Disconnect.Detect
SS.Disabled State
General Description
Exit Rules For The SS.Disabled State
Requirements For The SS.Disabled.Default Substate
Exit Rules For The SS.Disabled.Default Substate
Exit Rules For The SS.Disabled.Error Substate
13 Link Commands
Four Groups Of Link Commands
Link Commands On The SuperSpeed Link
For Additional Details On Link Commands
Link Command Encoding And Use
Packet Acknowledgement: LGOOD_n
Packet Acknowledgement: LBAD
Packet Acknowledgement: LRTY
Flow Control: LCRD_x
Power Management: LGO_Ux (The Request)
Power Management: LAU (Acceptance)
Power Management: LXU (Rejection)
Power Management: LPMA (Acknowledgement)
Link Up/Link Down: LDN
Link Up/Link Down: LUP
Notes On Link Command Placement
14 Header Packet Processing
Link Layer Packet Processing Role
Link Layer Transmitter Packet Processing
Header Sequence Number Assignment
Header Link Control Word CRC-5 Generated
Header CRC-16 Generated
Copy Is Placed In A Header Packet Buffer
Data Packet Payload CRC-32 Generation
General
Tx DPP CRC-32 Generation, The Hardware Details
Framing Added, Packet Sent To Physical Layer
Receiver Packet Processing
Inbound Link Layer Traffic
Key Header Packet Processing Elements
Header Packet CRC-16 Checked
Header Link Control Word CRC-5 Checked
Header Sequence Number Checked
Header Packet Buffer Accepts The Header
Data Packet Payload (DPP) CRC-32 Checked
General
Rx DPP CRC-32 Checking, The Hardware Details
15 Header Packet Flow Control
Background: Host And Device Flow Control
USB 2.0 Flow Control, Very Limited
The SuperSpeed Flow Control Approach
End To End Flow Control
Link Level Flow Control Is Also Needed
SuperSpeed Link Level Flow Control Basics
Flow Control Elements
Transmitter Elements
Tx Header Packet (HP) Buffers
Remote Rx HP Credit Count
Credit HP Timer
Next Rx LCRD_x
Receiver Elements
Rx Header Packet (HP) Buffers
LCRD_x Generation
Header Packet Flow Control Link Commands
General
LCRD_x Link Command Format
Flow Control Initialization
Flow Control Logic State After Reset
Flow Control Logic Initialization
Flow Control During Normal Operations
The First Header Is Sent
Header Packet Reaches Rx HP Buffer
Emptying An Rx HP Buffer
Transmitter Receives LCRD_x
If Tx Receives A Valid LCRD_x
If Tx Receives An Invalid LCRD_x
16 Link Errors & Packet Acknowledgement
Background: USB 2.0 Error Handling
USB 3.0 SuperSpeed Requires A New Approach
SuperSpeed Signaling Affects Bit Error Rates
Complex USB Topologies A Challenge At 5 Gb/s
Upstream Asynchronous Message Errors
Scope Of SuperSpeed Link Errors
Training Sequence Errors
Errors Occurring While Link is in U0
SuperSpeed Link Level Error Correction Approach
Goals Of Header Packet Acknowledgement
Reliable Delivery Of Header Packets
Hand Off The More Serious Errors
End-To-End Acknowledgement Is Still Needed
Header Packet Acknowledgement Elements
Transmitter Elements
HDR Seq# Assignment
Next Tx HDR Seq#
HDR CRC-5
HDR CRC-16
Tx HP (Header Packet) Buffers
Pending_HP_Timer
Next Rx LGOOD_n
Receiver Elements
HDR CRC-5 And CRC-16 Checks
Retries (Retry attempt counter)
LBAD Generation
HDR Seq# Check
Next Rx HDR Seq#
Rx Header Packet (HP) Buffers
LGOOD_n Generation
Header Packet Acknowledgement Link Commands
LGOOD_n Link Command Format
LBAD Link Command Format
LRTY Link Command Format
Header Packet Acknowledgement Initialization
HP Acknowledgement Logic After Reset
HP Sequence Number Advertisement
General
Sequence Of Events
HP Acknowledgement Sequence: No Retry Required
First Header Packet Is Sent
Header CRC-5, CRC-16 Checked By The Receiver
Header Sequence Number Checked By Receiver
Receiver Accepts And Acknowledges The Packet
Transmitter Checks LGOOD_n Acknowledgement
LGOOD_n Valid: Retire Header Packet
HP Acknowledgement Sequence: Retry Required
The Header Packet Is Sent
Header CRC-5 or CRC-16 Check Fails, LBAD Sent
Transmitter Receives LBAD, Starts The Retry
Retry Header Packet CRC-5, CRC-16 Checked
Retry Header Packet Sequence Number Checked
Receiver Acknowledges The Retry Header Packet
Transmitter Checks LGOOD_n Following The Retry
LGOOD_n Valid: Retire The Header Packet
17 Introduction to Chip-To- Chip Protocol
Chip-To-Chip Protocol And The Physical Layer
The Big Protocol Picture, Once More
Chip-To-Chip Protocol: PHY Logical Processing
A Note About D/K Bytes And Symbols
A Few Common Structure D/K Examples
The Physical Layer: PHY Logical Processing
Tx Scrambling
Tx 8b/10b Encoding
Tx Serialization
Rx Clock/Data Recovery
Rx De-serialization
Rx Elastic Buffer
Rx 8b/10b Decoding
Rx De-scrambling
Receiver PHY Forwards Traffic to Link Layer
The Physical Layer: PHY Electrical Specifications
General Topics
Transmitter PHY Electrical Topics
Receiver PHY Electrical Topics
Low Frequency Periodic Signaling (LFPS)
18 Physical Layer Logical Functions
Physical Layer Logic Definitions
Tx Physical Layer (PHY) Logic
Tx Outbound Bytes And The D/K Flag
Data Scrambling
General
Disabling Scrambling
8b/10b Encoding
The Purpose Of Encoding
Two Key 8b/10b Encoding Rules
Some 8b/10b Encoding Examples
8b/10b Encoding And Current Running Disparity
The AC-Coupled SuperSpeed Link
Advantages of AC-Coupling
Challenges of AC-Coupling
8b/10b Encoding Minimizes Disparity
An Example
Is The Transmitter CRD Choice Correct?
Parallel To Serial Data Conversion
Differential Transmitter
Rx Physical Layer (PHY) Logic
Differential Receiver And Equalization
Clock And Data Recovery
Clock Recovery
Data Recovery Circuit (DRC)
Serial To Parallel Data Conversion
Serial To Parallel Conversion and COM Symbol Lock
Differential Polarity Inversion (If Needed)
Elastic Buffer
Tx And Rx Clock Requirements
5 GHz Base Clock
Spread Spectrum Clocking
Implications Of Tx, Rx Clock Difference
The Result: Two Rx Clock Domains
Receiver PHY Clock Domain Notes
Elastic Buffer Architecture
Skip (SKP) Ordered Sets
8b/10b Decode
Error Checking At The Decoder
Decoded Data (D) And Control (K) Bytes
Descrambling Of Data (D) Bytes
Forwarding Traffic To Link Layer
19 SuperSpeed Reset Events
PowerOn Reset
Software May Enable And Disable VBUS
PowerOn Reset Impact On Device State
PowerOn Reset And Self-Powered Devices
Warm Reset
How Warm Reset Is Signaled On The Link
After Warm Reset Completes
Hot Reset
How Hot Reset Is Signaled On The Link
After Hot Reset Completes
Hot Reset, The LTSSM View
General Description
Requirements In Hot Reset.Active
Exit Rules For Hot Reset.Active
Requirements In Hot Reset.Exit
Exit Rules For Hot Reset.Exit
Notes About Warm Reset And Hot Reset Latency
Warm Reset Is Time Consuming, But Thorough
Hot Reset Is Much Faster, Not As Thorough
How Does Software Know If Hot Reset Is Possible?
The Two In-Band Reset Hub Requests
SetFeature (BH_PORT_RESET)
SetFeature (PORT_RESET)
Hubs Propagate Resets Downstream
General
Hub Reset Propagation, Key Rules
20 Link Training
Link Training Required Before SuperSpeed Operation
USB Physical Connections Complicate Link Training
The Long Channel
The Short Channel
SuperSpeed Link Training Is Adaptive
Which Logic Requires Training?
General
Summary Of Key Link Training Elements
Receiver Equalization
Clock Recovery
Data Recovery Circuit (DRC)
Serial To Parallel Conversion and Symbol Lock
Differential Polarity Inversion (If Needed)
Elastic Buffer Initialization
Link Training Is Managed by LTSSM
The Normal Link Training Sequence
Rx.Detect.Reset
Normal Exit From Rx.Detect.Reset
Other Exits From Rx.Detect.Reset
Rx.Detect.Active
SuperSpeed Receivers Enable & Disable Termination
Receiver Common Mode Input Impedance Range
The Detection Method
Normal Exit: From Rx.Detect.Active To Polling
Alternative Exit: From Rx.Detect.Active To Rx.Detect.Quiet
Other Exits From Rx.Detect.Active
Rx.Detect.Quiet
Polling.LFPS
The Polling.LFPS Burst Format
Other Polling.LFPS Requirements And Options
Normal Exit: From Polling.LFPS To Polling.RxEQ
Other Exits From Polling.LFPS
Polling.RxEQ
Other Requirements In Polling.RxEQ
The TSEQ Ordered Set
Two Special Symbols In TSEQ
Symbol K28.5 (COM)
Symbol 16-31 D10.2
Normal Exit: From Polling.RxEQ To Polling.Active
Polling.Active
Other Requirements In Polling.Active
The TS1 Ordered Set
Normal Exit: From Polling.Active To Polling.Configuration
Other Exits From Polling.Active
Polling.Configuration
The TS2 Ordered Set
Normal Exit: From Polling.Configuration To Polling.Idle
Other Exits From Polling.Configuration
Polling.Idle
General
Other Requirements In Polling.Idle
LGOOD_n Advertisement
General
Format Of LGOOD_n Link Command
LCRD_x Advertisement
General
Format Of LCRD_x Link Command
Port Capability LMP
Port Capability LMP Header Format
Link Speed Field (DW0, bits 15:9)
Num HP Buffers Field (DW1, bits 7:0)
D (Port Direction Support) Field (DW1, bits 17:16)
Tiebreaker Field (DW1, bits 23:20)
Port Configuration LMP
Port Configuration LMP Header Format
Selected Link Speed Field (DW0, bits 15:9)
Port Configuration Response LMP
Port Configuration Response LMP Header Format
Response Code Field (DW0, bits 15:9)
Link Training Is Complete, What Now?
General
Life In U0, A Few More Rules
21 Link Recovery and Retraining
Reasons For Link Recovery And Retraining
Recovery And Retraining Managed By The LTSSM
Recovery Is Speedy
Which Logic Is Retrained In Recovery?
Entering Recovery: Two Common Examples
U1-U3 Exit And Transition To Recovery
U0 Link Layer Error And Transition To Recovery
The Recovery Substate Events
Recovery.Active
Other Requirements In Recovery.Active
Recovery.Active And The TS1 Ordered Set
Two Special Symbols In TS1 Ordered Sets
Symbol K28.5 (COM)
Symbol 6-15 D10.2
Normal Exit: Recovery.Active To Recovery.Configuration
Other Exits From Recovery.Active
Recovery.Configuration
Recovery.Configuration And The TS2 Ordered Set
Normal Exit: From Recovery.Configuration To Recovery.Idle
Other Exits From Recovery.Configuration
Recovery.Idle
General
Other Requirements In Recovery.Idle
LGOOD_n Advertisement
A Simple Example
Format Of LGOOD_n Link Command
LCRD_x Advertisement
General
A Simple Example
For More Details On The LTSSM Recovery
22 Device Configuration
Overview
Standard Device Requests
Device Detection and Reporting
Device Detection Process - Details
Status Change Indicator (Endpoint 1)
Hub Port Status and Change Indicators
Get Port Status Request
Clear Port Connection Request
The Device Configuration Process
Address Device
Getting the Descriptors
General
Standard Descriptors
Device Descriptor
Descriptor Length and Type
DeviceClass/SubClass/Protocol
Maximum Payload Size for Endpoint Zero (EP0)
String Index Values
BOS Descriptor
USB 2.0 Extension
SuperSpeed USB Device Capability
Container ID
Configuration Descriptor
Number of Interfaces
Configuration Value
Attributes and Maximum Power
Interface Association Descriptor
Interface Descriptors
General
Interface Number and Alternate Setting
Endpoint Descriptors
Endpoint Companion Descriptor
String Descriptors
Setting Device Configuration
Additional Requests
Class Driver Initialization
23 SuperSpeed Hub Configuration
Configuring the Hub
Standard Device Requests
Hub Class Requests
Device Detection and Reporting
General
Device Detection Process
Status Change Endpoint (Endpoint 1)
Hub Port Status and Change Indicators
Get Port Status Request
Clear Port Requests
The Hub Configuration Process
Addressing the Device
Getting Descriptors
General
Get Device Descriptor
BOS Descriptor
USB 2.0 Extension
SuperSpeed USB Device Capability
Container ID
Configuration Descriptor
Configuration Value
Bus- or Self-Powered Hub
Maximum Bus Power Consumed
Hub’s Interface Descriptor
Status Change Endpoint Descriptor
General
Hub Status Change Endpoint Address/Transfer Direction
Status Change Endpoint Companion Descriptor
String Descriptors
Additional Requests
Hub Driver Initialization
Hub Class Descriptor
Power Switching Mode Implemented
Over-Current Protection Mode
Maximum Bus Current for Hub Controller
Device Removable/Non-removable
Hub-Specific Requests
Set Hub Depth
Port U1/U2 Timeout
Set Port Remote Wake Mask
Port Link State
Set Port Power
Port Reset
BH Port Reset
Hub Status Change Endpoint Request
Reading the Hub Status Field
Reading Hub Port Status
Summary of Hub Feature Selectors
24 SuperSpeed Power Management
Principles of SuperSpeed Power Management
Background
Power Management Design Goals
Link Power Management
Function Power Management
Suspend/Resume (U3)
SuperSpeed Link Power Management
The Link Power States
Link-Power Hierarchy
Software Role in Link Power Management
Host Software Triggers
Hub Inactivity Timers
U1 Inactivity Timeouts
U2 Inactivity Timeouts
U0 Æ U1 Æ U2 with Silent Transition
Device-Specific Inactivity Timers/Algorithms
Upstream and Downstream U1/U2 Triggers
The Handshake Sequence
Entering The U1 or U2 States
U1 / U2 Handshake and Timer Behavior
Device Suspend - U3
General
Entering SuperSpeed Suspend
The U3 Handshake
Device Suspend State
U1/U2/U3 Exit to U0
Triggering U1/U2/U3 Exit
The Exit Handshake Sequence and Timing
The HandShake
Wake Notification
Function Suspend
General
The Function Suspend Request
Latency Tolerance Message Reporting
Software Calulates Exit Latencies
Device Reports Current Latency
25 SuperSpeed Signaling Requirements
Physical Layer Electrical Signaling Scope
Normative And Informative Specifications
Jitter Budgeting (Informative)
General
Jitter Budget Allocations
SuperSpeed Voltage Levels, Some Definitions
SuperSpeed Transmitter Requirements
Tx Electrical Specifications
Normative Tx Electrical Parameters
Informative Tx Electrical Parameters
Transmitter Low Power Option
Transmitter De-emphasis
Background
Transmitter Signal De-emphasis Helps
Transmitter Spread Spectrum Clocking (SSC)
SuperSpeed Receiver Requirements
Rx Electrical Specifications
Normative Rx Parameters
Informative Rx Parameters
Rx Equalizer Training
SuperSpeed Receiver Termination
Receiver Common Mode Input Impedance Range
The Detection Method
Low Frequency Periodic Signaling Requirements
LFPS Is A Simple Squarewave
Six LFPS Signaling Event Types
LFPS Electrical Requirements
Transmitter And Receiver DC Specifications
High Impedance Reflections (Normative)
ESD Protection (Informative)
Short Circuit Requirements (Informative)
26 Compliance Testing
Scope Of USB 3.0 Compliance Testing
Key Compliance Testing Documents
Compliance Testing Resources: Documentation
Compliance Testing Resources: Hardware/Software
The Compliance Testing Environment
Key Test Suite 1: USB Command Verifier Compliance
General Approach USB Command Verification Tests
Test Assertions
USB Device State Test Assertions
Generic Device Operation Test Assertions
USB Device Request Test Assertions
USB Descriptor Definition Test Assertions
Nineteen Tests Used In USB Command Verification
Key Test Suite 2: Link Layer Compliance
General Approach In Link Layer Compliance Tests
Test Assertions
Link Management & Flow Control Test Assertions
Link Error Rules & Recovery Test Assertions
Link Reset Test Assertions
LTSSM Test Assertions
Protocol Layer Test Assertions
Hub Port Test Assertions
Forty Tests Are Used In Link Layer Testing
Electrical Compliance Testing
Factors Affecting USB Electrical Compliance Testing
Electrical Compliance And The Varied USB Topology
The Long Channel
The Short Channel
USB 3.0 Adds Even More Complexity
Electrical Compliance Test Support Is Designed-In
LTSSM Compliance Mode: Device Roles
Nine Compliance Mode Test Patterns
Electrical Compliance Testing And The LTSSM
27 Receiver Loopback Testing
Loopback Motivation
Standard Loopback Configuration
General Master And Slave Loopback Rules
The Loopback Test Pattern BERT Data (BDAT)
Optional Loopback Slave Error Counting Support
Loopback BERT Ordered Sets
BERT Reset (BRST)
BDAT Error Count Request (BERC)
BDAT Error Count (BCNT) Value
Slave BERT Command Processing Rules
General
BRST & BERC If No Slave Error Counting Support
Loopback And The LTSSM
General
Loopback LTSSM Substates And Transition Events
Loopback.Active Substate
Loopback.Exit Substate
A Note About Differences In Loopback Exit Latency
Loopback May Also Be Used In Compliance Testing