Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors

Cover
Contents
Acknowledgements
Preface
Authors’ Biography
Professional leadership role in scientific community – editors
1 Introduction: secured co-processors for machine learning and DSP applications using biometrics
1.1 Security of co-processors: an introduction, hardware threats, and conventional security solutions
1.2 Role of behavioral synthesis design process in security of co-processors
1.3 Introduction to ML co-processors and their security
1.3.1 What are ML algorithms and their co-processors
1.3.2 Why modern systems need ML co-processors and why to secure them
1.3.3 Role of behavioral synthesis in designing and securing ML co-processors
1.4 Introduction to DSP co-processors and their security: a behavioral synthesis perspective in designing and securing DSP co-pr
1.5 Biometric security for ML and DSP co-processors
1.5.1 How biometric security for hardware authentication is different than a user authentication
1.5.2 Why biometric security is required for hardware protection: advantages over traditional security mechanisms
1.5.3 Types of different physical biometric-based mechanisms for hardware security
1.6 Questions and exercise
References
2 Integrated defense using structural obfuscation and encrypted DNA-based biometric for hardware security
2.1 Introduction
2.2 Background on DNA/genome sequencing
2.3 State-of-the-art: discussion and analysis
2.3.1 Hardware steganography
2.3.2 Hardware watermarking
2.3.3 Hash-based digital signature
2.4 Integrated defense using structural obfuscation and encrypted DNA-based biometric for hardware security
2.4.1 Extracting DNA signature from IP vendor body sample
2.4.2 Encryption of the DNA signature using DES algorithm
2.4.3 Encoding of the encrypted DNA signature for conversion into secret constraints for hardware security
2.4.4 Embedding of the secret DNA signature into design
2.5 Detection/validation of embedded encrypted DNA signature in RT level design
2.6 Discussion and analysis
2.6.1 Security properties/parameters of encrypted DNA signature
2.6.2 Security analysis of structural obfuscation
2.6.3 Security analysis of encrypted DNA signature
2.6.4 Design cost analysis
2.7 Conclusion
2.8 Questions and exercise
References
3 Facial signature-based biometrics for hardware security and IP core protection
3.1 Introduction
3.2 Importance of HLS for designing DSP co-processors
3.3 Alternative techniques used for IPP of DSP co-processors
3.3.1 Fingerprint biometric
3.3.2 Hardware watermarking and steganography
3.3.3 Hash-based digital signature
3.4 Features of facial biometrics for IPP and its advantages over fingerprint biometrics
3.5 Summary of facial biometric methodology for IPP
3.6 Details of facial biometric methodology for IPP
3.6.1 Capturing facial biometric of IP vendor and subjecting to a specific grid size and spacing
3.6.2 Generate facial nodal feature points
3.6.3 Assign naming convention on facial nodal feature points
3.6.4 Determining feature dimensions
3.6.5 Generating facial signature for IP vendor-defined feature order
3.7 Security properties of facial biometric methodology for hardware security
3.8 Analysis and discussion
3.8.1 Analyzing the security strength based on varying facial signature
3.8.2 Security analysis
3.9 Conclusion
3.10 Questions and exercise
References
4 Secured convolutional layer hardware co-processor in convolutional neural network (CNN) using facial biometric
4.1 Introduction
4.2 Why to design secured CNN convolutional layer co-processor IP core?
4.3 Benefits of the approach
4.4 Summary of existing approaches in the literature
4.5 Background on CNN framework
4.6 Overview of the approach for designing a secured CNN convolutional co-processor IP core using facial biometric
4.7 Details of the approach
4.7.1 HLS flow of the approach for designing secured convolutional hardware IP core in CNN
4.7.2 Constructing DFG of CNN convolutional IP core
4.7.3 Scheduling the IP core design and generating register allocation information
4.7.4 Details of generating facial biometric signature
4.7.5 Demonstration of securing IP core through facial biometric
4.7.6 Data path synthesis
4.7.7 Demonstration of the methodology
4.8 Analysis and discussion
4.8.1 Analyzing the convolutional IP core design in terms of computation of pixels
4.8.2 Analyzing the change in resources (Muxes and Demuxes) of RTL datapath design post-implanting facial biometric signature of
4.8.3 Analyzing the security strength
4.8.4 Analyzing the design area
4.9 Conclusion
4.10 Questions and exercise
References
5 Handling symmetrical IP core protection and IP protection (IPP) of Trojan-secured designs in HLS using physical biometrics
5.1 Introduction
5.2 Contemporary approaches for symmetric IP core protection
5.2.1 Symmetrical IP core protection in HLS using watermarking and fingerprinting
5.3 HLS-based symmetrical IP core protection using IP buyer fingerprint biometric and IP seller facial biometric
5.3.1 Summary
5.3.2 Deriving fingerprint security constraints of IP buyer
5.3.3 Deriving facial security constraints of IP seller
5.3.4 Embedding the fingerprint security constraints of IP buyer in DSP design
5.3.5 Embedding the facial security constraints of IP seller in IP buyer fingerprint biometric-embedded DSP design
5.4 Protecting an IP seller (vendor) right against false ownership claim using facial biometric signature
5.5 Protecting an IP buyer’ right using fingerprint biometric signature
5.6 Detecting IP piracy before integration into SoC systems
5.7 Employing facial biometric for protecting Trojansecured SoC design against piracy
5.7.1 Threat model
5.7.2 Summary
5.7.3 Designing Trojan-secured design architecture
5.7.4 Generating facial signature-driven secret constraints for hardware security
5.7.5 Embedding the extracted facial security constraints into Trojan-secured design
5.8 Analysis and discussion
5.8.1 Analyzing security and design cost of symmetric IP core protection using facial and fingerprint biometric for DSP applicat
5.8.2 Analyzing security and design cost overhead of facial biometric embedded Trojan-secured DSP design
5.9 Conclusion
5.10 Questions and exercise
References
6 Palmprint biometrics vs. fingerprint biometrics vs. digital signature using encrypted hash: qualitative and quantitative compari
6.1 Introduction
6.2 Threat model
6.3 Fingerprint biometric for IPP of DSP coprocessors:
6.3.1 Summary of fingerprint biometric
6.3.2 Details of fingerprint biometric methodology
6.3.3 Embedding of fingerprint biometric signature on FIR filter
6.3.4 Detection and validation of fingerprint biometrics for detective control against IP piracy and nullifying fraud claim of I
6.4 Palmprint biometric for IPP of DSP coprocessors
6.4.1 Summary of approach
6.4.2 Embedding of palmprint biometric signature on FIR filter
6.4.3 Detection and validation of palmprint biometric for detective control against IP piracy and nullifying fraud claim of IP o
6.5 Digital signature using encrypted hash for IPP of DSP coprocessors
6.5.1 Summary of approach
6.5.2 Details of the approach
6.6 Qualitative comparison between fingerprint biometric for IPP vs. digital signature for IPP, digital signature for IPP vs. pa
6.7 Analysis and discussions of results
6.8 Conclusion
6.9 Questions and exercise
References
7 Secured design flow using palmprint biometrics, steganography, and PSO for DSP coprocessors
7.1 Introduction
7.2 Emerging and contemporary approaches for IP core protection (IPP)
7.3 Threat model and PSO-driven design space exploration
7.3.1 PSO-driven design space exploration in HLS
7.3.2 Advantage of PSO over other search space algorithms
7.4 Palmprint biometric-based hardware security approach
7.4.1 Overview of the low-cost palmprint-based hardware security approach
7.4.2 Details of the palmprint-based hardware security approach
7.5 Low-cost steganography-based hardware security approach
7.5.1 Overview of the low-cost steganography-based hardware security approach
7.5.2 Details of steganography-based hardware security approach
7.6 Designing low-cost secured DCT core datapath using discussed methodologies
7.6.1 Mathematical framework (transfer function for DCT core)
7.6.2 Designing DCT core datapath using low-cost palmprint biometric hardware security
7.6.3 Designing DCT core datapath using low-cost steganographic-based hardware security
7.7 Analysis and discussions
7.7.1 Design cost analysis of low-cost palmprint biometricbased security approach
7.7.2 Design cost analysis of low-cost steganography-based security approach
7.7.3 Security analysis of low-cost palmprint biometricbased security approach
7.7.4 Security analysis of low-cost steganography-based security approach
7.8 Conclusion
7.9 Questions and exercise
References
8 Methodology for exploration of security–design cost trade-off for signature-based security algorithms
8.1 Introduction
8.2 Why perform security–design cost trade-off?
8.3 Summary of “Signature based Security Algorithms for Hardware IPs” in the literature
8.4 Methodology for exploration of security–design cost trade-off for signature-based security
8.4.1 Summary
8.4.2 Details
8.5 Analysis and discussion
8.5.1 Security analysis
8.5.2 Analyzing the impact of signature strength on fitness value and register count for DSP applications
8.5.3 Analyzing the security algorithms in terms of hardware cost, embedded security constraints, and exploration time
8.6 Conclusion
8.7 Questions and exercise
References
9 Taxonomy of hardware security methodologies: IP core protection and obfuscation
9.1 Introduction
9.2 Possible hardware threats and attacks in the design flow of hardware IC
9.3 Taxonomy representation of IP core protection methodologies
9.3.1 Watermarking-based hardware security approach
9.3.2 Steganography-based hardware security approach
9.4 Taxonomy representation of obfuscation methodologies
9.4.1 Structural obfuscation-based security approach
9.4.2 Functional obfuscation-based security approach
9.5 Low-cost steganography-based hardware security approach
9.6 Comparison between various hardware security methodologies
9.7 Conclusion
9.8 Questions and exercise
References
Index
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