This book provides a state-of-the-art guide to Machine Learning (ML)-based techniques that have been shown to be highly efficient for diagnosis of failures in electronic circuits and systems. The methods discussed can be used for volume diagnosis after manufacturing or for diagnosis of customer returns. Readers will be enabled to deal with huge amount of insightful test data that cannot be exploited otherwise in an efficient, timely manner. After some background on fault diagnosis and machine learning, the authors explain and apply optimized techniques from the ML domain to solve the fault diagnosis problem in the realm of electronic system design and manufacturing. These techniques can be used for failure isolation in logic or analog circuits, board-level fault diagnosis, or even wafer-level failure cluster identification. Evaluation metrics as well as industrial case studies are used to emphasize the usefulness and benefits of using ML-based diagnosis techniques.
Author(s): Patrick Girard , Shawn Blanton, Li-C. Wang
Publisher: Springer
Year: 2023
Language: English
Pages: 319
City: Cham
978-3-031-19639-3
1
Contents
978-3-031-19639-3_1
Prerequisites on Fault Diagnosis
1 Defect, Fault, Error, Failure
2 Test Basics
2.1 Manufacturing Test and Field Test
2.2 Logic Test
2.2.1 Design for Test (DFT)
2.2.2 Fault Simulation
2.2.3 Test Generation
2.3 Memory Test
2.4 Analog / Mixed-Signal Test
2.5 SoC Test
2.6 Board Test
3 Volume Diagnosis for Yield Improvement
3.1 Failing Data Limitation in ATE and Its Impact to Diagnosis Accuracy and Resolution
3.2 How to Collect Failure Data for Diagnosis?
3.3 Failing Data Format
3.4 Volume Diagnosis Server Farm Setup to Process Thousands of Failing Data in Production Flow
3.5 Beside Failing Data Per Die, What Other Data to Collect for Statistics Yield Analysis
4 Fault Diagnosis of Customer Return
5 Yield and Profitable Quality (Changed from Initial ToC)
6 Conclusions
References
978-3-031-19639-3_2
Conventional Methods for Fault Diagnosis
1 Introduction
1.1 What Are Debug and Diagnosis?
1.2 Where Is Diagnosis Used?
1.3 IC-Level Debug and Diagnosis
1.4 Silicon Debug Versus Defect Diagnosis
2 Design for Debug and Diagnosis
3 Logic Design for Debug and Diagnosis (DFD) Structures
3.1 Scan
3.2 Observation-Only Scan
3.3 Observation Points with Multiplexers
3.4 Array Dump and Trace Logic Analyzer
3.5 Clock Control
3.6 Partitioning, Isolation, and De-featuring
3.7 Reconfigurable Logic
4 The Diagnosis Flow and Process
4.1 Diagnosis Techniques and Strategies
5 Automated Logic Diagnosis Using Scan
5.1 How Diagnosis Works
5.2 A Typical Diagnosis Flow
5.3 Making Diagnosis Work in a Full Work Flow
6 Improving Fault Diagnosis for Accuracy, Precision and Resolution
6.1 The Case for Opens
6.2 The Case for Bridges
6.3 Diagnosing At-Speed Failures
6.4 Cell Internal Defect or Interconnect Defect?
6.5 Defects in Scan Chains
6.6 Further Improving Resolution by Reducing Suspects
7 The Next Step: Machine Learning in Diagnosis
8 Summary and Future Challenges
References
978-3-031-19639-3_3
Machine Learning and Its Applications in Test
1 Introduction
2 Basic Concepts of Machine Learning
2.1 Supervised Learning
2.2 Unsupervised Learning
2.3 Reinforcement Learning
3 Popular Algorithms for Machine Learning
3.1 Linear Regression
3.2 Logistic Regression
3.3 Support Vector Machines (SVM)
3.4 Support Vector Regression (SVR
3.5 Artificial Neural Networks (ANNs)
3.6 Recurrent Neural Networks (RNNs)
3.6.1 Long Short-Term Memory Networks (LSTM)
3.7 Convolutional Neural Networks (ConvNets / CNNs)
3.8 Graph Neural Networks (GNNs)
3.9 Reinforcement Learning (RL)
3.9.1 Policy Iteration
3.9.2 Value Iteration
3.9.3 Model Based Monte Carlo
3.9.4 Model Free Monte Carlo
4 Applications in Test
5 Conclusion
References
978-3-031-19639-3_4
Machine Learning Support for Logic Diagnosis and DefectClassification
1 Introduction
2 Variations Versus Defects
2.1 Marginalities and Reliability
2.2 Variation-Aware Defect Characterization at Cell Level
2.3 Circuit Level Defect Characterization
2.4 Random Forests for Resistive Open Classification
2.4.1 Classification Errors
2.4.2 Decision Trees
2.4.3 Classification with Random Forests
2.4.4 Generating Training Sets
2.5 How Far We Are
3 Neural Networks for Defect Classification
3.1 Defect Classification Overview
3.2 Feature Extraction
3.3 Neural Network Training
3.4 Classification During Volume Test
3.5 How Far We Are
4 Bayesian Belief Networks for Intermittent Fault Identification
4.1 Modeling Intermittent Faults
4.2 Session-Based Diagnosis
4.3 Some Background on Bayesian Belief Networks
4.4 Intermittent Fault Identification with BBNs
4.4.1 BBNs for Diagnosis
4.4.2 Intermittent Fault Classification
4.5 How Far We Are
References
978-3-031-19639-3_5
Machine Learning in Logic Circuit Diagnosis
1 Introduction
2 Pre-Diagnosis
2.1 Diagnosis Outcome Preview Through Learning
2.2 Adaptive Test Pattern Reordering for Accurate Diagnosis
2.3 Test-Data Volume Optimization for Diagnosis
3 During Diagnosis
3.1 LearnX: A Deterministic-Statistical Single Defect Diagnosis Methodology
3.2 MD-LearnX: A Deterministic-Statistical Multiple Defect Diagnosis Methodology
3.3 Improving On-Chip Diagnosis Accuracy via Incremental Learning
4 Post Diagnosis
4.1 Diagnosis Quality Enhancement Through Learning
4.2 Automated On-ATE Debug of Scan Chain Failures
4.3 Automatic Classification of Bridge Defects
4.4 DFM Evaluation Using IC Diagnosis Data
4.5 LASIC: Layout Analysis for Systematic IC-Defect Identification using Clustering
5 Conclusions
References
978-3-031-19639-3_6
Machine Learning Support for Cell-Aware Diagnosis
1 Introduction
2 Background on Conventional Cell-Aware Generation, Test and Diagnosis
3 Learning-Based Cell-Aware Model Generation
3.1 Generation of Training and New Data
3.2 Cell and Defect Representation in the Cell-Aware Matrix
3.2.1 Identification of Active and Passive Transistors
3.2.2 Renaming of Transistors
3.2.3 Identification of Parallel Transistors
3.2.4 Defect Representation
3.3 Support of Sequential Cells
4 Advanced Cell-Aware Diagnosis Based on Machine Learning
4.1 Preliminaries and Test Scenarios
4.2 Learning-Based Cell-Aware Diagnosis Flow
4.2.1 Generation of Training Data
4.2.2 Generation of Instance Tables
4.2.3 Generation of New Data
4.2.4 Diagnosis of Defects in Sequential Cells
5 Applications on Industrial Cases
5.1 CA Model Generation Results
5.1.1 Predicting Defect Behavior on the Same Technology
5.1.2 Predicting Defect Behavior on Another Technology
5.1.3 Analysis and Discussion
5.1.4 Hybrid Flow for CA Model Generation
5.2 CA Diagnosis Results
5.2.1 Simulated Test Case Studies
5.2.2 Silicon Test Case Studies
6 Conclusion and Discussion
References
978-3-031-19639-3_7
Machine Learning Support for Diagnosis of Analog Circuits
1 Introduction
2 Fault Modeling
3 Fault Simulation
4 Overview of Diagnosis Approaches for Analog Circuits
4.1 Rule-Based Diagnosis
4.2 Model-Based Diagnosis
4.2.1 Explicit Nonlinear Diagnosis Equations
4.2.2 Sensitivity Analysis
4.2.3 Behavioral Modeling
4.3 Fault Dictionary-Based Diagnosis
4.4 DfT-Assisted Diagnosis
4.5 Diagnosis with Defect Simulator in-the-Loop
4.6 Machine Learning-Based Diagnosis
5 Machine Learning Support
5.1 A Unified Diagnosis Flow Based on Machine Learning
5.2 Diagnostic Measurement Extraction and Selection
5.2.1 Extraction
5.2.2 Selection
5.3 Defect Filter
5.4 Parametric Fault Diagnosis Based on Regression Modeling
5.5 Fault Dictionary-Based Diagnosis Using Classifiers
6 Industrial Case Study
6.1 Device Under Test
6.2 Real Dataset
6.3 Fault Modeling
6.4 Fault Dictionary
6.5 Missing Values Problem
6.6 Classifiers
6.6.1 Pass/Fail Verification
6.6.2 Euclidean Distance
6.6.3 Mahalanobis Distance
6.6.4 Non-Parametric Kernel Density Estimation
6.6.5 Support Vector Machine
6.7 Diagnosis Results
7 Conclusion and Discussion
References
978-3-031-19639-3_8
Machine Learning Support for Board-Level Functional FaultDiagnosis
1 Introduction
1.1 Flow of Board-Level Manufacturing Test
1.2 Overview of Board-Level Fault Diagnosis
2 Machine Learning-Based Functional Fault Diagnosis
3 Board-Level Functional Fault Identification Using Streaming Data
3.1 Problem Formulation
3.2 Online Learning for Binary Classifiers
3.3 Fault Diagnosis Based on Multi-Class Classifiers
3.4 A Hybrid Algorithm for Streaming Data with Different Chunk Sizes
3.5 Experimental Results
4 Knowledge Transfer in Board-Level Functional Fault Identification
4.1 Problem Formulation
4.2 Knowledge Transfer for Binary Classifier
4.2.1 Similarity Evaluation
4.2.2 Homogeneous Domain Adaptation
4.2.3 Heterogeneous Domain Adaptation
4.3 Knowledge Transfer for Multi-Class Classifiers
4.3.1 Feature Extractor
4.3.2 Domain Alignment
4.3.3 Diagnosis Classifier
4.4 Experimental Results
5 Chapter Summary
References
978-3-031-19639-3_9
Machine Learning Support for Wafer-Level Failure Pattern Analytics
1 Introduction
1.1 A Yield Excursion Example
1.2 Detecting Yield Excursion
1.3 Detecting a Systematic Failure Cluster
1.3.1 Insight From Failure Analysis
1.4 Lessons Learned
1.4.1 Iterative Analysis
1.4.2 Systematic Issue
1.4.3 Plot Visualization
2 Wafer Map Pattern Recognition
2.1 The Multi-Class Classification Problem
2.2 Prior Works on the WM-811K Dataset
2.3 A Multi-Class Neural Network Classifier
2.3.1 Manual Review
2.3.2 Applied to Unlabeled Wafer Maps
2.4 Lessons Learned
2.4.1 Definition of Pattern Classes
2.4.2 The Quality of the Training Dataset
2.4.3 Optimization Vs. Personalization
3 Learning A Recognizer For A Pattern Class
3.1 Concept Recognition
3.1.1 The Robustness Concern
3.2 Use of Tensor-Based Methods
3.2.1 The Basic Ideas
3.3 An Application Result
3.4 Lesson Learned
4 Describable Analytics
4.1 IEA and Concept Recognition
4.2 Plot-Based Analytics
4.3 A ``Try-and-See'' Analytics Process
4.3.1 Usage of the App
4.4 Three Major Components
4.4.1 The Minions Approach
4.4.2 A Brief Note on Training a Minion
4.4.3 Primitive Pattern and Describable Set
4.5 The Frontend
4.6 Lesson Learned
References
1 (1)
Summary and Conclusions
Reference
Index
