Machine Learning for Embedded System Security

Preface
The Contents at Glance
Book Audience
Acknowledgments
Contents
About the Editor
Part I Machine Learning for Secure Hardware Design
1 Intelligent Anti-tamper Design for Embedded Systems Using Machine Learning
1.1 Introduction
1.2 Chapter Overview
1.3 Background
1.3.1 Attack Difficulty
1.3.2 Adversary Classification
1.3.3 Principles of CIST Threat Modeling Approach
1.3.4 A Primer on Hardware Tampering Attacks
1.3.4.1 Device Open
1.3.4.2 X-Ray
1.3.4.3 Fault Injection Attacks
1.3.5 Existing Tamper Defense Mechanisms
1.3.5.1 Tamper-Resistant Techniques
1.3.5.2 Tamper Detection
1.3.5.3 Tamper Response Mechanisms
1.3.5.4 Tamper Evidence
1.3.6 Standard Requirements for Physical Security
1.3.7 Multinomial Classification Using Machine Learning Algorithms
1.3.7.1 Support Vector Machine
1.3.7.2 Naive Bayesian Classifier
1.3.7.3 Stochastic Gradient Descent
1.3.7.4 K-Nearest Neighbor
1.3.7.5 Decision Tree
1.3.7.6 Random Forest
1.3.8 Anomaly Detection Using Machine Learning
1.3.8.1 One-Class Support Vector Machine
1.3.8.2 Nearest Neighbors
1.3.8.3 Local Outlier Factor
1.3.8.4 Cluster-Based Local Outlier Factor
1.3.8.5 Isolation Forest
1.3.8.6 Histogram-Based Outlier Score
1.4 Threat Modeling
1.4.1 Application Scenarios
1.4.2 Security Objectives
1.4.3 Identification of Threats
1.4.4 Attack Mechanisms
1.5 Proposed Countermeasure
1.5.1 Overview
1.5.2 Design Rationale
1.6 Experimental Setups
1.6.1 Design Architecture
1.6.2 Data Collection
1.6.2.1 Indoor Data Collection
1.6.2.2 Outdoor Data Collection
1.6.2.3 Attack Data Collection
1.7 Comparative Analysis of Machine Learning Algorithms
1.7.1 Comparison Metrics
1.7.2 Outlier Algorithms Comparison
1.7.2.1 Normal Behavior in an Indoor Environment
1.7.2.2 Outlier Models for Attack Scenario
1.7.3 Multi-class Algorithm Comparison
1.8 Prototype Testing
1.8.1 Procedure
1.8.2 Attack Detection Results
1.8.3 Energy Requirements
1.9 Security Validation
1.9.1 Critical Infrastructure Devices
1.9.2 Devices in Contested Environments
1.10 Conclusions
References
2 Machine Learning for Secure Hardware Design
2.1 Introduction
2.2 Chapter Overview
2.3 ML for Detection of IC Counterfeit
2.3.1 IC Counterfeit and Its Types
2.3.2 Counterfeit Detection Using ML Approaches
2.4 ML for Detection of Hardware Trojan
2.4.1 Hardware Trojan Threat
2.4.2 Hardware Trojan Detection Using ML Approaches
2.5 ML for Secure PUF Design: Attacks and Countermeasures
2.5.1 Overview on PUF
2.5.2 PUF Threat Model
2.5.3 Learning-Based Novel Attacks on PUFs
2.5.4 Secure PUF Construction: Learn from the Past
2.6 Challenges and Opportunities
2.7 Conclusion
References
3 The Physical Unclonable Functions Fight: State-of-the-Art Architectures and Their Performance Against Advanced Deep Learning Modeling Attacks
3.1 Introduction
3.2 Chapter Overview
3.3 Overview of Physical Unclonable Functions (PUFs)
3.3.1 Non-electronic PUFs
3.3.2 Electronic Intrinsic PUFs
3.3.2.1 Delay-Based Intrinsic PUFs
3.3.2.2 Memory-Based Intrinsic PUFs
3.3.2.3 Hybrid Intrinsic PUFs
3.3.2.4 Strong PUFs vs. Weak PUFs
3.3.3 PUF Properties
3.3.4 PUF Applications
3.3.4.1 Identification
3.3.4.2 Authentication
3.3.4.3 Key Generation
3.4 Overview of Attacks on PUFs
3.4.1 Machine Learning-Based Attacks
3.4.2 Hybrid Side-Channel/Machine Learning Attacks
3.4.3 Fault Injection Attacks
3.5 The Countermeasures Against ML Attacks
3.5.1 Implementation Enhancement of Delay-Based PUFs on FPGAs
3.5.1.1 Double Arbiter PUF
3.5.1.2 Randomly Generated APUF
3.5.2 New PUF Architectures Without Derived Mathematical Models
3.5.2.1 Bistable Ring PUFs
3.5.2.2 Obfuscation Techniques
3.6 DL Attacks
3.6.1 Modeling Attacks on Double Arbiter PUFs
3.6.1.1 Modeling Attacks on XOR Bistable Ring PUFs
3.6.2 Discussion on Successful DL Attacks and Countermeasures
3.6.3 The Practicality of the DL Attacks and Applications
3.6.4 N-to-1 Shuffled-Challenge Hierarchical PUF
3.7 Discussion and Future Work
3.8 Conclusion
References
Part II Machine Learning for Cyber-Physical System Security
4 Machine Learning for Cyber-Physical Power System Security
4.1 Introduction
4.2 Overview
4.3 The Framework of Attack vs. Defense in Cyber-Physical Power System
4.3.1 Attacking Methods in CPPS
4.3.1.1 Eavesdropping Attack
4.3.1.2 False Data Injection Attack
4.3.1.3 Distributed Denial of Service
4.3.2 Defending Framework in Cyber-Physical Power Systems
4.4 Application of Machine Learning for Cyber-Physical Power System Security
4.4.1 Preliminaries of FDI Attack in Power System State Estimation
4.4.1.1 State Estimation
4.4.1.2 False Data Injection Attack
4.4.2 Measurement Data Recovery in State Estimation Based on PG-SeqGAN
4.4.2.1 Generation Model
4.4.2.2 Training Process of PG-SeqGAN
4.4.2.3 Simulation Results
4.4.3 Identification of the Critical Vulnerability Based on Reinforcement Learning
4.4.3.1 Problem Formulation with Markov Decision Process
4.4.3.2 Problem Solution with Q-learning
4.4.3.3 Simulation Results
4.5 Conclusions
References
Part III Machine Learning for Embedded Systems Malware Analysis
5 Machine Learning for Malware Analysis in Embedded Systems
5.1 Introduction
5.2 Chapter Overview
5.3 Background
5.3.1 Detrended Fluctuation Analysis
5.3.2 Pearson's Correlation Coefficient
5.3.3 Mutual Information
5.3.4 Principal Component Analysis
5.3.5 Support Vector Machines
5.4 Related Work
5.5 Family Classification Methodology
5.5.1 Fingerprint Generation
5.5.2 Classification and Training
5.6 Architecture and Prototype Implementation
5.6.1 Architecture
5.6.2 Prototype Implementation
5.6.2.1 Tools' Integration
5.6.3 Performing Analysis on Real Devices
5.7 Experimental Evaluation
5.7.1 Datasets
5.7.2 Experiments on the Drebin Dataset
5.7.2.1 Experimental Setup
5.7.2.2 Time Requirements
5.7.2.3 Stability of the DFA exponent
5.7.2.4 SVM Training and Test
5.7.2.5 Results
5.7.2.6 Comparison with DroidScribe
5.7.3 Experiment on the AMD Dataset
5.7.3.1 Experimental Setup
5.7.3.2 Results
5.8 Conclusions
References
Index