Reese B. Logic Synthesis with VHDL Combinational Logic.
Учебное пособие на английском языке. Mississippi State University.-1995. - 46p
Без оглавления.
Use of Logic Synthesis has become common industrial practice.The advantages are many:
-Technology portability
- Design Documentation
- Constraint Driven Synthesis
Two major languages are Verilog and VHDL. This tutorial will conver logic synthesis via VHDL. We will split the tutorials into three parts:
-Introduction to VHDL via combinational synthesis examples
-Sequential synthesis examples (registers, finite state machines)
- System examples (combined datapath and control)
