Focussing on micro- and nanoelectronics design and technology, this book provides thorough analysis and demonstration, starting from semiconductor devices to VLSI fabrication, designing (analog and digital), on-chip interconnect modeling culminating with emerging non-silicon/ nano devices. It gives detailed description of both theoretical as well as industry standard HSPICE, Verilog, Cadence simulation based real-time modeling approach with focus on fabrication of bulk and nano-devices. Each chapter of this proposed title starts with a brief introduction of the presented topic and ends with a summary indicating the futuristic aspect including practice questions. Aimed at researchers and senior undergraduate/graduate students in electrical and electronics engineering, microelectronics, nanoelectronics and nanotechnology, this book:
- Provides broad and comprehensive coverage from Microelectronics to Nanoelectronics including design in analog and digital electronics.
- Includes HDL, and VLSI design going into the nanoelectronics arena.
- Discusses devices, circuit analysis, design methodology, and real-time simulation based on industry standard HSPICE tool.
- Explores emerging devices such as FinFETs, Tunnel FETs (TFETs) and CNTFETs including their circuit co-designing.
- Covers real time illustration using industry standard Verilog, Cadence and Synopsys simulations.
Author(s): Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik
Publisher: CRC Press
Year: 2020
Language: English
Pages: 372
City: Boca Raton
Cover
Half Title
Title Page
Copyright Page
Contents
List of Figures
List of Tables
List of Abbreviations
Preface
Authors
Acknowledgments
Chapter 1: Semiconductor Physics and Devices
1.1. Introduction
1.1.1. Conduction in Solids
1.1.2. Conductors, Insulators, and Semiconductors
1.1.2.1. Conductors
1.1.2.2. Insulators
1.1.2.3. Semiconductors
1.1.3. P-Type and N-Type Semiconductors
1.1.3.1. N-Type Semiconductors
1.1.3.2. P-Type Semiconductors
1.1.4. Semiconductor Conductivity
1.2. Diode
1.2.1. Diode Structure and Characteristics
1.2.2. PN Diode Structure
1.2.2.1. Forward and Reverse Bias Regions
1.2.3. Zener Diode Structure
1.2.4. Diode Applications
1.2.4.1. Rectifiers
1.2.4.2. Diode Logic Gates
1.2.4.3. Clipping and Clamping Circuits
1.3. Bipolar Junction Transistor
1.3.1. Symbol and Physical Structure
1.3.1.1. Operation and Several Current Components
1.3.2. BJT Configurations
1.3.2.1. Common Base (CB) Configuration
1.3.2.2. Common Emitter (CE) Configuration
1.3.2.3. Common Collector (CC) Configuration
1.3.2.4. BJT in CE Configuration: Operationand I–V Characteristic
1.3.3 Second-Order Effects
1.3.3.1. Base-Width Modulation
1.3.3.2. Recombination in the Depletion Region
1.3.3.3. Breakdown Mechanism in BJT
1.4. Field-Effect Transistor
1.4.1. Junction Field-Effect Transistor (JFET)
1.4.1.1. Symbol and Physical Structure
1.4.1.2. Operation of JFET
1.4.1.3. Current–Voltage Characteristics and Regions of Operation
1.4.2. Metal-Oxide-Semiconductor Field-Effect Transistor
1.4.2.1. Symbol and Device Structure
1.4.2.2. Device Operation
1.4.3. Advantages of MOSFET Over JFET
1.5. Emerging Devices Beyond CMOS
1.5.1. Issues with CMOS Technology Scaling
1.5.1.1. Velocity Saturation and Mobility Degradation
1.5.1.2. Tunneling Current Through Gate Insulator
1.5.1.3. High Field Effects
1.5.1.4. Power Limitation
1.5.1.5. Material Limitation
1.5.2. Emerging Nanoscale Device Technologies
1.5.2.1. Gate-All-Around (GAA) Nanowire (NW) MOSFET
1.5.2.2. Fin Field-Effect Transistor (FinFET)
1.5.2.3. Carbon Nanotube FETs (CNTFETs)
1.5.2.4. Tunnel FET (TFET)
1.6. Summary
1.7. Multiple-Choice Questions
1.8. Small Answer Questions
1.9. Long Answer Questions
References
Chapter 2: VLSI Scaling and Fabrication
2.1. Introduction to VLSI Scaling
2.1.1. History and Introduction of VLSI Technology
2.1.2. VLSI Design Concept
2.1.3. Moore’s Law
2.1.4. Scale of Integration
2.1.5. Types of VLSI Chips (Analog and Digital)
2.1.6. Layout, Micron, and Lambda Rules
2.2. Vlsi Fabrication Process
2.2.1. Purification, Crystal Growth, and Wafer Processing (CZ and FZ Process)
2.2.1.1. Introduction
2.2.1.2. Electronic Grade Silicon
2.2.1.3. Czochralski Crystal Growing
2.2.1.4. Silicon Shaping
2.2.2. Oxidation
2.2.2.1. Introduction
2.2.2.2. Growth Mechanism
2.2.2.3. Oxidation Techniques and Systems
2.2.2.4. Redistribution of Dopants at Interface
2.2.2.5. Oxidation of Polysilicon
2.2.3. Epitaxial Deposition
2.2.3.1. Introduction
2.2.3.2. Vapor-Phase Epitaxy
2.2.3.3. Molecular Beam Epitaxy
2.2.3.4. Silicon on Insulator
2.2.4. Lithography
2.2.4.1. Introduction
2.2.4.2. Optical Lithography
2.2.4.3. Electron Beam Lithography
2.2.4.4. X-ray Lithography
2.2.5. Polysilicon and Dielectric Deposition
2.2.5.1. Deposition Process
2.2.5.2. Polysilicon
2.2.5.3. Silicon Dioxide
2.2.5.4. Silicon Nitride
2.2.6. Diffusion
2.2.6.1. Introduction and Model of Diffusion
2.2.6.2. Flick’s First Law of Diffusion
2.2.6.3. Diffusion Factors
2.2.6.4. Diffusivity in Polycrystalline Silicon and SiO2
2.2.7. Ion Implantation
2.2.7.1. Introduction
2.2.7.2. Range Theory
2.2.7.3. Implantation Equipment
2.2.7.4. Annealing
2.2.8. Metallization
2.2.8.1. Choice of Metal
2.2.8.2. Metallization Process
2.2.8.3. Metallization Problem
2.2.8.4. New Approaches Toward Metallization
2.2.9. Etching Process
2.2.9.1. Dry or Plasma Etching
2.2.9.2. Wet Etching
2.3. Basic Cmos Technology
2.3.1. N-Well and P-Well CMOS Process
2.3.2. Twin-Tub Process
2.4. Summary
2.5. Multiple-Choice Questions
2.6. Short Answer Questions
2.7. Long Answer Questions
References
Chapter 3: MOSFET Modeling
3.1. Introduction to MOS Transistor
3.1.1. Characteristics of MOS Transistor
3.1.2. Hot Carrier Effects
3.1.3. Parasitics of MOSFET
3.1.4. MOSFET Circuit Models
3.2. Mos Capacitor
3.2.1. MOS Capacitor with Zero and Nonzero Bias
3.2.2. Capacitance-Voltage Curves
3.2.3. Anomalous Capacitance-Voltage Curves
3.3. MOSFET DC and Dynamic Models
3.3.1. Pao-Sah Model
3.3.2. Charge Sheet Model
3.3.3. Piece-Wise Model for Enhancement Devices
3.3.4. Small Geometry Model
3.3.5. Intrinsic Charges and Capacitance
3.3.6. Meyer Model
3.4. MOSFET Modeling Using SPICE
3.4.1. Basic Concepts of Modeling
3.4.2. Model Equations
3.4.2.1. Level 1 Model Equation
3.4.2.2. Level 2 Model Equation
3.4.2.3. Level 3 Model Equation
3.4.2.4. BSIM Model
3.4.3. Examples Using HSPICE
3.5. Summary
3.6. Multiple-Choice Questions
3.7. Short Answer Questions
3.8. Long Answer Questions
References
Chapter 4: Combinational and Sequential Design in CMOS
4.1. CMOS Inverter
4.1.1. Design
4.1.2. Operation
4.1.3. Transient and VTC Characteristics
4.1.4. Significance of the CMOS Inverter
4.2. Static Behavior of the Inverter
4.2.1. Switching Threshold
4.2.2. Noise Margin
4.2.3. Robustness of the CMOS Inverter By Scaling Supply Voltage
4.3. Dynamic Behavior of CMOS Inverter
4.3.1. Capacitances
4.3.1.1. Gate-Drain Capacitance
4.3.1.2. Diffusion Capacitance (Cdb1, Cdb2)
4.3.1.3. Gate Capacitance (Cg3, Cg4)
4.3.1.4. Propagation Delay of the CMOS Inverter
4.3.2. Power and Energy Consumption
4.3.2.1. Power Consumption
4.3.2.2. Dynamic Power Consumption
4.3.2.3. Static Power Consumption
4.3.2.4. Direct Path Power Consumption
4.3.2.5. Total Power Consumption
4.4. Design of Combinational Logic Design
4.4.1. Complementary CMOS Logic
4.4.1.1. Guidelines in Designing Static CMOS Logic
4.4.1.2. Two- and Multi-Input Static Complementary Gates
4.4.1.3. Sizing Static Complementary Gates for optimum Propagation Delay
4.4.2. Ratioed Logic
4.4.2.1. Differential Cascade Voltage Switch Logic (DCVSL)
4.4.3. Pass-Transistor Logic
4.4.3.1. Differential Pass Transistor Logic
4.4.3.2. Transmission Gate Logic
4.5. CMOS Sequential Design
4.5.1. Introduction
4.5.2. Metrics for CMOS Sequential Design
4.6. Static Latches and Registers
4.6.1. The Bistability Principle
4.6.2. SR Flip-Flops
4.6.3. D-latches and Flip-Flops
4.6.4. Master-Slave Flip-Flop
4.7. Summary
4.8. Multiple-Choice Questions
4.9. Short-Answer Questions
4.10. Long-Answer Questions
References
Chapter 5: Analog Circuit Design
5.1. Introduction to Analog Design
5.2. MOS Device from Analog Perspective
5.2.1. I/V Characteristics
5.2.2. Second-Order Effects
5.2.2.1. Body Effect
5.2.2.2. Channel-Length Modulation
5.2.2.3. Subthreshold Conduction
5.2.3. MOS Small Signal Model
5.3. Single-Stage Amplifier
5.3.1. Common Source
5.3.2. Common Gate
5.3.3. Source Follower
5.4. Current Mirrors
5.4.1. Introduction
5.4.2. Basic Current Mirror
5.4.3. Cascode Current Mirror
5.5. Differential Amplifiers
5.5.1. Single-Ended and Differential Operation
5.5.2. Basic Differential Pair
5.5.2.1. Input–Output Characteristics
5.5.3. Differential Pair With MOS Load
5.6. Operational Amplifier
5.6.1. Fundamentals and General Op-amp Metrics
5.6.2. Two-Stage Op-amp
5.7. Digital-to-Analog and Analog-to-Digital Converters
5.7.1. Introduction
5.7.1.1. DAC: Digital-to-Analog Converter
5.7.1.2. ADC: Analog to Digital Converter
5.7.2. Types of Digital-to-Analog Converters
5.7.2.1. Weighted Resistor DAC
5.7.2.2. Weighted Capacitor DAC
5.7.3. Types of Analog-to-Digital Converters
5.7.3.1. Flash Converters
5.7.3.2. Successive-Approximation ADC (SA ADC)
5.8. Summary
5.9. Multiple-Choice Questions
5.10. Short Answer Questions
5.11. Long Answer Questions
References
Chapter 6: Digital Design Through Verilog HDL
6.1. Introduction
6.1.1. What Is Verilog HDL?
6.1.2. Background
6.1.3. Compiler Directives
6.1.4. Data Types
6.1.5. Operators
6.1.5.1. Arithmetic Operator
6.1.5.2. Equality Operators
6.1.5.3. Relational Operators
6.1.5.4. Logical Operators
6.1.5.5. Bitwise Operators
6.1.5.6. Conditional Operator
6.1.5.7. Concatenation Operator
6.2. Module and Test Bench Definitions
6.2.1. Module
6.2.2. Test Bench
6.3. Gate-Level Modeling
6.3.1. Built-In Primitives
6.3.2. Single and Multiple Input Gates
6.3.3. Tristate Gates
6.3.4. MOS Switches
6.3.5. Gate Delays
6.3.6. Example
6.4. Dataflow Modelling
6.4.1. Continuous Assignment
6.4.2. Delays
6.4.3. Examples: A Verilog Program for Full Adder
6.5. Behavioral Modeling
6.5.1. Initial Statement
6.5.2. Always Statement
6.5.3. Procedural Assignments
6.5.3.1. Blocking Procedural Assignment
6.5.3.2. Nonblocking Procedural Assignment
6.5.4. Conditional Statements
6.5.5. Loop Statements
6.5.5.1. For-Loop Statement
6.5.5.1. While-Loop Statement
6.5.5.3. Forever-Loop Statement
6.5.6. Examples
6.6. Tasks and Functions
6.6.1. Task
6.6.2. Function
6.7. Summary
6.8. Multiple-Choice Questions
6.9. Short Answer Questions
6.10. Long Answer Questions
References
Chapter 7: VLSI Interconnect and Implementation
7.1. An Overview of the VLSI Interconnect Problem
7.1.1. Interconnect Scaling Problem
7.1.2. Implementation of Interconnect Problem
7.2. Interconnect Aware Design Methodology and Electrical Modeling
7.2.1. Impact of Scaling
7.2.2. Transistor Scaling
7.2.3. Interconnect Scaling
7.3. Electrical Circuit Model of Interconnect
7.3.1. Ideal Interconnect
7.3.2. Resistive Interconnect
7.3.3. Capacitive Interconnect
7.3.4. Resistive Interconnect Tree
7.4. Estimation of Interconnect Parasitics
7.4.1. Interconnect Resistance Estimation
7.4.2. Interconnect Inductance Estimation
7.4.3. Interconnect Capacitance Estimation
7.4.3.1. Parallel Plate Capacitor
7.4.3.2. Fringing Capacitance
7.4.3.3. Lateral Capacitance
7.5. Calculation of Interconnect Delay
7.5.1. RC Delay Model
7.5.2. Elmore Delay Model
7.5.3. Transfer Function Model Based on ABCD Parameter Matrix
7.5.4. Finite Difference Time Domain Model
7.6. Estimation of Interconnect Crosstalk Noise
7.7. Estimation of Interconnect Power Dissipation
7.8. Summary
7.9. Multiple-Choice Questions
7.10. Short Answer Questions
7.11. Long Answer Questions
References
Chapter 8: VLSI Design and Testability
8.1. Preamble
8.2. Basic Digital Troubleshoot
8.2.1. Manufacturing Test
8.2.2. Tester and Test Fixtures
8.2.3. Test Programs
8.3. Effect of Physical Faults on Circuit Behavior
8.3.1. Fault Models
8.3.1.1. Line Stuck-at Faults
8.3.1.2. Transistor Stuck-at Faults
8.3.1.3. Floating Line Faults
8.3.1.4. Bridging Faults
8.4. Test Principles of Manufacturing
8.4.1. Observability
8.4.2. Controllability
8.4.3. Fault Coverage
8.4.4. Automatic Test Pattern Generation (ATPG)
8.4.5. Delay Fault Testing
8.5. Test Approaches
8.5.1. Ad Hoc DFT Techniques
8.5.2. Scan Design Test
8.5.3. Built-in Self-Test (BIST)
8.5.4. IDDQ Testing
8.6. Design for Manufacturability (DFM)
8.7. System On Chip (SOC) Testing
8.8. Summary
8.9. Multiple-Choice Questions
8.10. Short Answer Questions
8.11. Long Answer Questions
References
Chapter 9: Nanomaterials and Applications
9.1. Preamble of Nanomaterials
9.2. Introduction to Carbon Nanotubes
9.2.1. The Concept of Chirality on CNT
9.2.2. Electronic Band Structure
9.2.3. Brillouin Zone
9.3. Overview of Graphene Nanoribbon
9.4. Properties of CNT and GNR
9.5. Fabrication Approaches for Graphene Nanostructure
9.5.1. The Transfer Process of Graphene on the Si/SiO2 Substrate
9.5.2. CNT Fabrications
9.6. Application of Nanomaterials
9.6.1. Graphene Nanoribbon Interconnect
9.6.1.1. Geometry of MLGNR Interconnect
9.6.1.2. Equivalent MTL Model of MLGNR Interconnect
9.6.1.3. ESC Model of MLGNR Interconnect
9.6.1.4. Validation of MTL and ESC Model
9.6.1.5. Simulation Setup of MLGNR
9.6.1.6. Crosstalk-Induced Delay Analysis
9.6.2. Carbon Nanotube-Based Interconnect
9.6.2.1. Interconnect Model
9.6.2.2. Performance Comparison
9.6.3. Nanosensor
9.6.3.1. Flexible Sensor
9.6.3.2. Nanosensor for Biomedical Applications
9.6.4. Nanomaterial-Based Combat Jackets
9.6.5. Nano-Biosensors for Drug Delivery
9.7. Summary
9.8. Multiple-Choice Questions
9.9. Short Answer Questions
9.10. Long Answer Questions
References
Chapter 10: Nanoscale Transistors
10.1. Issues with CMOS Technology Scaling
10.1.1. Velocity Saturation and Mobility Degradation
10.1.2. Tunneling Limit
10.1.3. High Field Effects
10.1.4. Power Limitation
10.1.5. Material Limitation
10.2. Tunnel FET
10.2.1. Device Structure and Models
10.2.2. Device Characteristics
10.2.2.1. TFET as ON Switch
10.2.2.2. Ambipolar Characteristics
10.2.2.3. Unidirectional Characteristics and p-i-n Forward Leakage
10.2.3 TFET-Based Circuit Design
10.2.3.1. TFET-Based Static Complementary Inverter Design
10.2.3.2. TFET-Based Digital Buffer Design
10.3. Negative Capacitance FET
10.3.1. Device Structure
10.3.2. Principle of Operation
10.3.3. Low Subthreshold Swing and High ON Current
10.3.4. Hysteresis Characteristics
10.3.5. NCFET Device-Based Inverter and Digital Logic Design
10.4. Carbon Nanotube FET
10.4.1. Carbon Nanotube
10.4.2. Carbon Nanotube FET
10.4.3. Device Characteristics
10.5. Graphene Nanoribbon FET
10.5.1. Graphene Structure and Properties
10.5.1.1. Mechanical Properties
10.5.1.2. Electrical Properties
10.5.2. Graphene Nanoribbon FET
10.5.2.1. Graphene Nanoribbon
10.5.2.2. Graphene Nanoribbon FET
10.6. Spintronic Devices
10.6.1. Principle of Operation
10.6.2. Spin-Based Devices
10.6.2.1. STT MTJs
10.6.2.2. GSHE-Based Devices
10.6.2.3. ASL Devices
10.7. Summary
10.8. Multiple-Choice Questions
10.9. Short Answer Questions
10.10. Long Answer Questions
References
MCQ Answers
Index
