This book explains mechanical and thermal reliability for modern memory packaging, considering materials, processes, and manufacturing.
In the past 40 years, memory packaging processes have evolved enormously. This book discusses the reliability and technical challenges of first-level interconnect materials, packaging processes, advanced specialty reliability testing, and characterization of interconnects. It also examines the reliability of wire bonding, lead-free solder joints such as reliability testing and data analyses, design for reliability in hybrid packaging and HBM packaging, and failure analyses. The specialty of this book is that the materials covered are not only for second-level interconnects, but also for packaging assembly on first-level interconnects and for the semiconductor back-end on 2.5D and 3D memory interconnects.
This book can be used as a text for college and graduate students who have the potential to become our future leaders, scientists, and engineers in the electronics and semiconductor industry.
Author(s): Chong Leong Gan, Chen-Yu Huang
Series: Springer Series in Reliability Engineering
Publisher: Springer
Year: 2023
Language: English
Pages: 222
City: Cham
Preface
Acknowledgements
Contents
About the Authors
1 Advanced Memory and Device Packaging
1.1 Introduction
1.2 Wire Bonding in Memory Packaging
1.3 Technical Challenges with Memory Device Packaging
1.3.1 Key Challenges with Wire Bonding in Memory Packaging
1.4 Evolutions of Interconnects Materials in Memory Packaging
1.4.1 Evolution of Bonding Wires for Memory Packaging
1.4.2 Evolution of Solder Alloys for Memory Packaging
1.5 Evolutions of Polymeric Materials in Memory Packaging
1.5.1 Evolution of Die Attach Film (DAF) for Memory Packaging
1.5.2 Evolution of Non-conductive Film (NCF) for Memory Packaging
1.5.3 Evolution of Encapsulant Materials for Memory Packaging
1.5.4 Evolution of Underfill (UF) for Flip-Chip Memory Packaging
1.6 Memory Packaging Reliability
1.6.1 Package Reliability Tests
1.7 Summary and Recommendations
References
2 Wearout Reliability-Based Characterization in Memory Packaging
2.1 Introduction
2.2 Concept of Reliability
2.3 Key Fatigue Failure Models and Characteristics
2.3.1 Wearout Failure Mechanisms in Memory Packaging
2.4 First Level Interconnect Wearout Reliability
2.4.1 Ball Bond Reliability in Wire Bonding
2.4.2 Bump and Solder Joint Reliability in Flip Chip Packaging
2.5 Wearout Reliability Studies in Memory Packaging
2.5.1 Solder Joint Reliability
2.5.2 Board Level Drop Test
2.5.3 Monotonic Board Level Bending Test
2.5.4 Implications of Monotonic Bending Test for Memory Mobile Applications
2.6 Cyclic Board Level Bending Test on Memory Modules
2.6.1 Criteria and Test Conditions
2.7 Summary and Recommendations
References
3 Recycling of Noble Metals Used in Memory Packaging
3.1 Introduction
3.2 Possibility of Recycling Noble Metals in Packaging
3.3 Key Enablers of Semiconductor Packages with Recycled Materials
3.3.1 Review Methodology
3.4 Recycling and Recovery of Nobel Metals in Semiconductor Assembly
3.4.1 Recycling of Gold in Semiconductor Packaging
3.4.2 Recycling of Cu in Semiconductor Electronics
3.4.3 Recycling of Sn in Semiconductor Electronics
3.5 Co-existence of Prime and Recycled Bonding Wires in Semiconductor Industry
3.5.1 Recycled Materials Reliability Perspective
3.5.2 Comparison of Materials Cost and Reliability: Recycled Au Wire with Prime Wire
3.5.3 Interconnect Reliability with Recycled Wire in Semiconductor Packaging
3.6 Key Recycling Initiative by Industry Semiconductor Manufacturers
3.6.1 Key Recycling Initiatives
3.7 Summary and Recommendations
References
4 Advanced Flip Chip Packaging
4.1 Introduction
4.2 Flip-Chip Chip Scale Package (FCCSP) Application in Memory Packages
4.3 Process and Reliability Failure Modes in Flip-Chip Memory Packages
4.3.1 Thin Die Warpage Induced Joint Failure
4.3.2 Cu Pillar Bump Abnormality
4.4 Flip Chip Bonding Technology
4.4.1 Mass Reflow
4.4.2 TCB (Thermal Compression Bonding)
4.4.3 Tack, Gang and Collective Bonding
4.4.4 LAB (Laser Assisted Bonding)
4.5 Flip Chip Interconnection Types of Memory Packages
4.5.1 Types of Cu Pillar Bump
4.5.2 Substrate Technology in Flip-Chip Memory Package
4.6 Advanced Heterogeneous Integration for HBM
4.6.1 2.1D Technology
4.6.2 2.3D Technology
4.6.3 2.5D Technology
4.6.4 EMIB Technology
4.6.5 Si Bridge Technology
4.7 Summary and Recommendations
References
5 Second Level Interconnect Reliability of Low Temperature Solder Materials Used in Memory Modules and Solid-State Drives (SSD)
5.1 Introduction
5.2 Second Level Interconnects
5.2.1 Solder Joint Interfacial Reactions (Surface Finish and the Formation of Intermetallic Compounds)
5.3 Shear Strength of Interfacial IMCs
5.3.1 Kirkendall Effects and Formation of Kirkendall Voiding
5.4 Solder Joint Reliability
5.4.1 Requirements for Hand-held Application
5.4.2 Requirements for Computing Application
5.4.3 Automotive Applications
5.5 Low Temperature Solder Paste (LTS)
5.5.1 Why LTS?
5.5.2 Types of LTS
5.5.3 Benefits of LTS in Memory Module Reliability Performances
5.5.4 Interconnect Reliability with Low Temperature Solders
5.6 Factors Influencing Solder Joint Reliability (SJR)
5.6.1 SJR Performances of Memory Modules and SSDs
5.6.2 Factors Impacting Board Level Drop Performance
5.6.3 Construction Analysis and Solder Joint Characterization
5.7 Reliability Requirements on Solid State Drive (SSD) and Memory Modules
5.7.1 Standard Reliability Requirements
5.7.2 Extended Reliability Requirements
5.8 Potential Applications of LTS for Advance Packaging
5.9 Summary and Recommendations
References
6 Specific Packaging Reliability Testing
6.1 Introduction
6.2 Package Strength Characterization of Memory Packages
6.2.1 Methodologies Used for MCP Strength Evaluation
6.2.2 Effect of Material Properties on Package Strength
6.2.3 Effect of Warpage on Package Strength
6.2.4 Effect of Package Construction on Package Strength
6.2.5 Failure Analysis of Package After Bending Break
6.3 Board Level Drop Test: Strain Measurement for Memory Package on Printed Circuit Board
6.4 Chip Package Interaction (CPI) Assessment on Cu Pillar Bump
6.5 Soft Error Rate (SER) and Alpha Emission Rate (AER) in Memory Packages
6.5.1 AER of Package Materials and Characterization Metrologies
6.5.2 Study of Alpha Particle Induced Memory Failure
6.6 Summary and Recommendations
References
7 Reliability Simulation and Modeling in Memory Packaging
7.1 Introduction
7.2 Simulation for Wire Bonding and Stacked-Die Packages
7.2.1 Wire Bonding Interconnection Reliability
7.2.2 Thermal–Mechanical Reliability of Multi-die Stacked Package
7.2.3 Stacked Die Reliability Issue
7.2.4 Three-Point Bending and Four-Point Bending Simulations
7.3 Simulation for Solder Joint Reliability of Memory Package
7.3.1 Plastic Work Accumulation of BGA Package During Thermal Cycling
7.4 Simulation for Flip Chip Memory Packages
7.4.1 The Effect of Cu Pillar Patterns on FCCSP Memory Reliability
7.4.2 Mold Flow Simulation
7.5 Simulation for Stacked-Die Memory with TSV
7.6 Alpha Particle Emission Simulation in Memory Device
7.7 Summary and Recommendations
References
8 Interconnects Reliability for Future Cryogenic Memory Applications
8.1 Introduction
8.2 Why is There a Need of Cryogenic Memory?
8.3 Immersion Cooling Technology
8.4 Module Packaging for Quantum Computing
8.4.1 Module Packaging for High Performance Computing
8.4.2 Key Challenges and Reliability Considerations with S-MCM in Cryogenic Temperature
8.5 New Materials for Cryogenic Memory
8.5.1 Solder Joint Evolutions at Cryogenic Temperature (CT)
8.5.2 Implications of Solder Joint Brittle Fracture and Mechanical Performance in High Performance Computing Applications
8.6 Characterization of Solders at Cryogenic Temperature
8.6.1 Behavior of Solder Alloys and Polymers at Cryogenic Conditions
8.7 Materials/Memory Modules for Quantum Computing
8.8 Reliability Evaluation for Cryogenic Memory Packages
8.9 Recent Progress by Key Industrial Players
8.10 Recent Progress of Industry Initiatives in Cryogenic Memory Computing
8.11 Summary and Recommendations
References
Index
