Complex Digital Hardware Design

Cover
Half Title
Title Page
Copyright Page
Table of Contents
About the Author
Chapter 1 Introduction
Book Organization
Chapter 2 Digital Circuits
2.1 I/O Standards
2.1.1 Terminations and Reflections
2.1.2 PAM4 versus NRZ Signaling
2.1.3 Level Translation
2.1.4 Protocols
2.2 JTAG
2.3 External Parallel Interface
2.3.1 Synchronous Mode
2.3.2 Asynchronous Mode
2.3.3 Wait States
2.3.4 Multi-Master Arbitration
2.4 SERDES IP
2.4.1 SERDES Signals
2.4.2 Tile Architecture
2.4.3 Transmit Signal Path
2.4.4 Receive Signal Path
2.5 Button or Switch Debouncing
2.6 ESD
2.7 Data Corruption
2.7.1 SEU
2.8 Security
Chapter 3 Major Interfaces
3.1 Ethernet
3.1.1 Protocol
3.1.2 External and Backplane Ports
3.1.3 MAC-PHY Interfaces
3.1.4 Optical Ethernet Ports
3.1.5 Base-T Type Ethernet Coupling
3.2 PCI and PCIe
3.2.1 The PCI Bus
3.2.1.3 PCI-X
3.2.2 PCI Express
3.2.3 Configuration
3.3 Common HB Interfaces
3.3.1 SATA
3.3.2 USB 3.0
3.3.3 Computer Video
3.3.4 JESD204x
3.3.5 Data Center Chassis-to-Chassis Interconnects
3.4 High Performance Computing Links
Chapter 4 Power Supply Circuits
4.1 Global Power Circuits
4.1.1 Chassis Input Power
4.1.2 Board Input Power
4.2 Voltage Regulator Modules (VRM)
4.2.1 VRM Architectures
4.2.2 Basic Buck VRM Operation
4.2.3 Strapping and Settings
4.2.4 VRM Chip Features
4.2.5 VRM Control Loop Types
4.2.6 Feedback Loop Compensation
4.2.7 VRM Analysis
Chapter 5 Components
5.1 Resistors
5.2 Capacitors
5.3 Inductors
5.4 LEDs
5.5 Transistor Circuits
5.6 Small Logic ICs
5.7 Super I/O Chips
5.8 Clocking Chips
5.9 PHY and Gearbox Chips
5.10 Retimer Chips
5.11 Peripheral Controllers
5.11.1 Ethernet NIC
5.11.2 SATA/SAS Controller Chips
5.11.3 USB Chips
5.12 PCIe Bridging and Switching
5.12.1 PCI-to-PCI Bridges (P2PB)
5.12.2 PCIe-to-PCI Bridges (PE2PB)
5.12.3 PCIe Switches (PESW)
5.12.4 Configuring the Devices
5.12.5 Switch Devices for Other Protocols
5.13 High-Speed ADCs
5.14 Basic Connectors
5.15 High-Speed Connectors
5.16 Optical Cage Connectors
5.17 Mechanical Parts
5.17.1 Heatsinks
5.18 Flyover Cables
5.19 Memory
5.19.1 Non-volatile Memories
5.19.2 Volatile Memories
5.19.3 DDRx SDRAM Types
Chapter 6 Main Chips
6.1 Processors
6.1.1 Microcontrollers
6.1.2 ARM Processors
6.1.3 DSPs
6.1.4 PowerPC
6.1.5 Soft Processors
6.1.6 X86 CPUs and Chipsets
6.2 FPGAs
6.2.1 FPGA Basics
6.2.2 FPGA Families
6.2.3 FPGA Resources
6.2.4 FPGA Pinout Planning
6.2.5 Development Flow
6.3 ASICs
6.3.1 Ethernet Switch ASICs
6.3.2 GPUs
6.3.3 AI ASICs
6.3.4 Accelerator ASICs
6.3.5 Search and TCAM ASICs
Chapter 7 Hardware Architecture
7.1 Building Blocks
7.2 Computers
7.2.1 System Buses
7.2.2 System Initialization
7.2.3 Registers
7.3 Data Plane
7.4 Control Plane
7.5 Glue Logic
7.5.1 The Use of IP Cores
7.5.2 Power Management
7.5.3 Power Sequencing
7.5.4 Resets
7.5.5 Interrupts
7.6 System Management
7.6.1 Hot Swapping and Hot Plugging
7.7 Power Subsystem
7.8 Clocking Scheme
7.8.1 Time Synchronization
7.8.2 RTC
7.9 Multi-board Architectures and Backplanes
7.10 Design Examples
7.10.1 The Tioga Pass Node Server Motherboard
7.10.2 The Minipack-2 SMB Switch Card
7.10.3 The VXS DSP FMC Carrier Card
Chapter 8 Systems and Chassis
8.1 Form Factors
8.1.1 Working with Mechanical Engineering
8.1.2 Thermal
8.2 Consumer, Industrial, Scientific
8.3 Military/Aerospace Hardware
8.4 Telecom Equipment
8.5 Data Center Hardware
8.5.1 What Is in a Data Center
8.5.2 Servers
8.5.3 Accelerators and Appliances
8.5.4 Network Switches
Chapter 9 Hardware-Firmware Integration
9.1 BIOS
9.1.1 BIOS Customization
9.1.2 ARM Bootloaders
9.2 Custom OS Image
9.2.1 Device Drivers
9.3 Working with a Data Plane FPGA Team
9.4 Test Software
9.5 System Management Firmware
9.5.1 Temperature Thresholds Settings
Chapter 10 Timing Analysis
10.1 Chip-Level Timing Analysis
10.1.1 Timing Constraints
10.2 Board-Level Timing Analysis
10.2.1 Basic Synchronous Data Path
10.2.2 Timing Parameters
10.2.3 Signal Integrity Analysis
10.2.4 Generalized Timing Equations
10.2.5 Complete System, Timing Graphs
10.3 Timing Architectures
10.3.1 Design Elements to Control Timing
10.3.2 Topology Diagrams
10.3.3 Main Interface Types
10.3.4 Custom Interfaces
10.3.5 DDRx SDRAM Memory
10.4 Timing-Driven PCB Trace Length Constraints
10.4.1 The Length Calculations
10.4.2 Architecture Specific Considerations
10.5 Summary Design Flow
10.5.1 Example: Synchronous SPI interface
10.6 Automating the Timing Calculations
Chapter 11 Signal Integrity
11.1 S-Parameters
11.1.1 RF Techniques for High-Speed Digital
11.1.2 Mixed-Mode S-Parameters
11.1.3 Derived S-Parameters
11.1.4 Margins
11.1.5 The Touchstone File Format
11.2 SI Basics
11.2.1 Transmission Lines
11.2.2 Crosstalk
11.2.3 Jitter
11.2.4 Stubs
11.2.5 Return Path
11.2.6 Impedance Discontinuities
11.3 SI Simulators
11.3.1 Simulation Basics
11.3.2 A Multi-stage View
11.3.3 Eye and BER
11.3.4 IBIS Models
11.3.5 SI Simulation Report
11.3.6 Layout Model Resolution
11.3.7 Examples of SI Simulators
11.4 Via Structure Impedance Optimization
11.4.1 Manufacturing and layout
11.4.2 HFSS
11.4.3 Simbeor
11.4.4 Via Issues on S-Parameter Profiles
11.5 SERDES Link Analysis
11.5.1 Analysis Domains
11.5.2 Channel Frequency Domain S-Parameters
11.5.3 Channel Time Domain TDR response
11.5.4 Signal Time Domain Eye Diagrams
11.5.5 Bit Error Counters and BER Tests
Chapter 12 PCB Materials and Stackups
12.1 Dielectric Materials
12.1.1 DK versus Frequency
12.2 Fiber Weave Effect
12.2.1 Rotation or Angle
12.2.2 Butter Coat
12.2.3 Diffpair Asymmetry
12.3 Trace Impedance Control
12.3.1 Frequency Dependent Impedance
12.3.2 Geometry
12.3.3 Impedance Measurements
12.3.4 Impedance Calculator Software
12.4 Insertion Loss Control
12.4.1 Copper Surface Roughness
12.4.2 Documentation
12.4.3 Loss Testing
12.5 Stackup Design
12.5.1 The Three Main Aspects of Stackup Design
12.5.2 Building the Layer Sequence
12.5.3 Crosstalk versus Stackup
12.6 Anisotropic Material Properties
12.6.1 Anisotropic DK
12.6.2 Anisotropic DF
12.7 Simulation to Measurement Correlation
12.7.1 Loss Tuning for Correlation
Chapter 13 Power Integrity
13.1 PI Introduction
13.2 Elements of PDN
13.2.1 VRMs
13.2.2 Decoupling Capacitors
13.2.3 Power Planes
13.3 Parasitic Inductances
13.4 Decoupling Methods
13.5 Rogue Waves
13.5.1 Known Methods of Estimating a Maximum Rogue Wave
13.5.2 Quality Factor
13.5.3 Automated PDN Design through Optimization
13.6 PDN Simulation
13.6.1 Pre-Layout PDN Analysis
13.6.2 Post-Layout PDN Analysis
13.6.3 Post-Prototype PDN Analysis
13.6.4 DC Voltage Drop Analysis
13.6.5 PDN-Related Simulators
Chapter 14 Initial Design
14.1 Preparations
14.1.1 The Proposal
14.1.2 The Plan
14.1.3 Component Selection
14.1.4 Project Schedule
14.2 Paradigm Shift
14.3 Typical Project Documentation
14.4 Floor Planning
14.4.1 Fitting the Pinout into the Floorplan
14.4.2 Fanout Analysis
14.4.3 Floorplan Investigation Example
14.5 Loss Budget Calculation
14.6 Design Notes
14.6.1 Connector Pinouts
14.7 Schematics
14.7.1 Schematics Readability
14.8 Design for Manufacturing (DFM)
14.9 Design for Test (DFT)
14.10 Design for Debugging (DFD)
Chapter 15 PCB Layout Design
15.1 Major CAD Tools
15.2 PCB Basics
15.2.1 Placement
15.2.2 Fanout
15.2.3 Routing
15.2.4 Tool Features
15.3 Density and Routing Channels
15.4 Constraints
15.5 PCB Manufacturability
15.5.1 VIA Usage
15.5.2 VIPPO VIAs
15.5.3 Through-Hole Parts
15.5.4 Solder Mask Expansion
15.5.5 Soldering in General
15.5.6 Fiducials
15.5.7 IPC Class 2 and 3
15.6 High-Speed Rules
15.6.1 Summary for SERDES Links
15.6.2 Summary for Non-SERDES Signals
15.7 Ground Return Path
15.7.1 Localization
15.8 High-Speed Escape Route
15.8.1 Escape Artistry
15.8.2 Layer Usage
15.8.3 Escape Route and Backdrilling
15.9 High-Speed VIA Design
15.9.1 Differential Design
15.9.2 Stub Removal
15.9.3 Via Impedance Control
15.9.4 Crosstalk Reduction
15.9.5 Via Design and Replication Summary
15.9.6 Connector Pin Field Guard Vias
15.10 AC-Coupling Capacitors
15.11 Memory Interfaces
15.11.1 DIMM Memory
15.11.2 Memory-Down
15.12 VRM Layout
15.13 Power Delivery
15.13.1 Filtered Rails
15.13.2 Voltage Sense Line Resistor Placement
15.13.3 Decoupling Capacitor Placement
15.14 Signal Swapping
15.15 PCB Layout Review
15.15.1 General component placement
15.15.2 High Speed
15.15.3 Plane Related
15.15.4 Mechanical
15.15.5 General
Chapter 16 Prototyping
16.1 Bring-Up Sequence
16.1.1 Test Software
16.1.2 PCI Scan
16.1.3 Ethernet Ports
16.1.4 Example of Prototype Bugs
16.2 Dongles
16.3 Test Fixtures
16.4 Live System Boundary Scan
16.5 Re-work
16.6 VRM validation
16.7 Transceiver Tuning
16.8 EMI Test
16.9 Design Verification Testing (DVT)
16.10 Mechanical Testing
Chapter 17 Measurements
17.1 Clock Measurements
17.2 On-Die Eye Scan
17.3 Oscilloscope Measurements
17.3.1 Tap-On Measurements
17.3.2 TDR Measurements
17.4 Signal VNA Measurements
17.4.1 Test Setup and Measurement
17.4.2 Preparation and Design Requirements
17.4.3 Fixture De-embedding
17.4.4 Probe Landing Issues
17.5 Power VNA Measurements
17.5.1 The Purpose of the Measurement
17.5.2 Test Setup
17.5.3 Power VNA Calibration
17.5.4 Probing Inductance
17.5.5 VNA Attachments
Chapter 18 Manufacturing
18.1 Manufacturability
18.2 Manufacturing Release
18.2.1 Components and BOM
18.2.2 Factory Selection
18.3 Production Testing
18.3.1 Device Programming
18.3.2 Functional Tests
18.3.3 Manufacturing Test/Debug Guidelines Document
18.3.4 Automation of Test and Programming
18.4 Production Issues
18.5 RMAs
18.6 Reliability
18.6.1 Product Failures
18.6.2 Design Margins
18.6.3 Statistics
References
Index