Analog Circuits for Machine Learning, Current/Voltage/Temperature Sensors, and High-speed Communication: Advances in Analog Circuit Design 2021

Preface
The Topics Covered Before in this Series
Contents
Part I Analog Circuits for Machine Learning
1 Mixed-Signal Compute and Memory Fabrics for Deep Neural Networks
1 Introduction
2 Efficiency Limits of Digital DNN Accelerators
3 Analog and Mixed-Signal Computing
4 In-Memory Computing
5 Discussion and Conclusions
References
2 Analog Computation with RRAM and Supporting Circuits
1 Introduction
2 Analog Crossbar Computation
3 Challenges of Crossbar Operation
3.1 Device Nonlinearity
3.2 Mixed-Signal Peripheral Circuitry
4 Non-volatile Crossbar Synapses
4.1 Flash
4.2 Filamentary Resistive-RAM
5 Digital RRAM Crossbar
5.1 Analog Operation with Digital RRAM Cells
6 Analog RRAM Crossbar
6.1 Analog Operation with Analog RRAM Cells
6.2 Fully Integrated CMOS-RRAM Analog Crossbar
6.2.1 RRAM Programming
6.2.2 RRAM Nonlinearity
6.2.3 CMOS Prototype
6.2.4 Measurement Setup
6.2.5 Single-Layer Perceptron Example
6.2.6 System Performance
7 Conclusions
References
3 Analog In-Memory Computing with SOT-MRAM: Architecture and Circuit Challenges
1 Introduction
2 Resistive Element Array
3 SOT MRAM Memory Element
4 SOT MRAM-Based Cell for AiMC
5 MVM Result in SOT Array
6 Impact of LSB Size on ADC Design
6.1 LSB Shrinking on CS SAR DAC
6.2 LSB Shrinking on CS SAR Comparator
7 Conclusions
References
4 Prospects for Analog Circuits in Deep Networks
1 Introduction
2 Review of Circuits for Analog Computing
3 Analog Circuits for Matrix-Vector Multiplication
4 Non-volatile Resistive Crossbars
5 Future of Analog Deep Neural Network Architectures
5.1 Trends in Machine Learning ASICs
6 Conclusion
References
5 SPIRIT: A First Mixed-Signal SNN Using Co-integrated CMOS Neurons and Resistive Synapses
1 Introduction
2 NVM Technology
3 Neural Network Architecture
3.1 Building a SNN
3.2 Learning Strategy
4 Circuit Architecture
4.1 Synapse Implementation
4.2 Neuron Design
4.3 Top Architecture
5 Measurement Results
5.1 Circuit Validation
5.2 Extra Measurements on OxRAMs
6 Discussion
7 Conclusion
References
6 Accelerated Analog Neuromorphic Computing
1 Introduction
2 Overview of the bss Neuromorphic Architecture
3 The hicannx Chip
3.1 Event-Routing Within hicannx
3.2 Analog Inference: Rate-Based Extension of hicannx
4 Analog Verification of Complex Neuron Circuits
4.1 Interfacing Analog Simulations from Python
4.2 Monte Carlo Calibration of adex Neuron Circuits
5 Conclusion
Author Contribution
References
Part II Current, Voltage, and Temperature Sensors
7 Advancements in Current Sensing for Future Automotive Applications
1 Introduction
2 Current Sensing
2.1 Classical Current Sensing
2.2 Improvement of Classical Current Sensing
2.3 From Linear to Switched Concepts
2.4 Current Sensing Goes Digital
2.5 Impact to Future Designs
3 Conclusions
References
8 Next Generation Current Sense Interfaces for the IoT Era
1 Introduction
2 Sensing Interfaces for IoT
2.1 Current Sensing
2.2 Capacitive Sensing
2.3 Inductive Sensing
2.4 Resistive Sensing
3 Multi-sense Interfaces
4 Choosing a Current Sensing ADC
4.1 Two-Step ADCs
4.2 Current Mode Incremental ADC (CI-ADC)
5 Incremental Δ Design Considerations
5.1 Choosing Both Coarse and Fine ADC Order
5.2 Understanding Noise
5.3 Incremental Δ Linearity with Passive Integrators
5.4 Capacitor Sizing
5.5 Decimation Filter
6 Multi-Sense with a CI-ADC
6.1 Current Sensing with a CI-ADC
6.2 Capacitive Sensing with a CI-ADC
6.3 Inductive Sensing with a CI-ADC
6.4 Resistive Sensing with a CI-ADC
7 Measurement Results
7.1 Optical Proximity Results
7.2 Capacitance Sensing Results
7.3 Inductive Sensing Results
7.4 Resistance Sensing
8 Conclusions
References
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges
1 ADC Overview
1.1 Sampling
1.2 Quantisation
1.3 Other Noise Sources
1.3.1 Aperture Error
1.3.2 Thermal Noise
1.4 ADC Signal to Noise
1.5 Figure of Merits
1.5.1 Walden FoM
1.5.2 Schreier FoM
1.6 Architecture Comparison
1.7 Architecture Selection
2 SAR ADC Architecture
3 Noise-Shaped SAR ADC
4 Error Feedback Design Example
5 Dynamic Amplifier
6 Conclusion
References
10 Breaking Unusual Barriers in Sensor Interfaces: From Minimum Energy to Ultimate Low Cost
1 Introduction
2 Ultra-Low Power All-Dynamic Multimodal Sensor Interface
2.1 Proposed All-Dynamic Versatile Sensing Platform
2.2 Low Power All-Dynamic Temperature Sensing
2.3 All-Dynamic Capacitance Sensor Interface
2.4 All-Dynamic 4-Terminal Resistance Sensor Interface
2.5 SAR ADC
2.6 Measurement Results
3 Ultimate Low-Cost Electronics
4 A Printed Smart Temperature Sensor for Cold Chain Monitoring Applications
4.1 System Architecture
4.2 Circuit Implementation
4.3 Measurement Results
5 Conclusions
References
11 Thermal Sensor and Reference Circuits Based on a Time-Controlled Bias of pn-Junctions in FinFET Technology
1 Introduction
2 Basic Principles
2.1 Bulk Diode Properties
2.2 Capacitive Bias of PN-Junctions
2.3 Forward-Bias Through Negative Charge-Pump
3 Application to a Switch-Cap Reverse Bandgap Reference
4 An Untrimmed Thermal Sensor Using Bulk Diodes for Sensing
4.1 Pulse-Controlled Sensor Principle
4.2 Circuit Realization with C-DAC
4.3 Simulation and Measurement Results
5 Conclusions
References
12 Resistor-Based Temperature Sensors
1 Introduction
2 Theoretical Energy Efficiency of Different Sensors
2.1 Temperature Sensors and Resolution FoM
2.2 BJT Sensor and Theoretical FoM
2.3 Resistor Sensor and Theoretical FoM
2.4 Effect of Readout Circuits
3 Resistor Choice and Sensor Topologies
3.1 Sensing Resistor Choice
3.2 Reference Choice
3.3 Dual-R Sensor Examples
3.4 RC Sensor Examples
4 An Energy-Efficient WhB Sensor Design
4.1 Front-End Design
4.2 Readout Circuit Design
4.3 Measurement Results
5 Summary
References
Part III High-speed Communication
13 Recent Advances in Fractional-N Frequency Synthesis
1 Introduction
2 Noise and Fractional-N Spurs
3 Divider Controller Spurs
4 Loop Nonlinearities
4.1 Loop Filter and Controlled Oscillator
4.2 Frequency Divider
4.3 Time Difference Measurement
5 Interaction Between the Divider Controller and Loop Nonlinearities
6 Spur Mitigation Strategies
7 All-Digital Phase Locked Loops
8 Conclusion
References
14 ADC/DSP-Based Receivers for High-Speed Serial Links
1 Introduction
2 ADC Resolution Requirements and Topologies
3 Digital Equalization
4 A 52 Gb/s ADC-Based PAM-4 Receiver with Comparator-Assisted 2 Bit/Stage SAR ADC and Partially Unrolled DFE
4.1 Receiver Architecture
4.2 ADC Design
4.3 DSP Design
4.4 Measurement Results
5 Conclusion
References
15 ADC-Based SerDes Receiver for 112 Gb/s PAM4 Wireline Communication
1 Introduction
2 ADC-Based Receiver Architecture
2.1 Peak to Main Cursor Ratio (PMR)
2.2 Distributed Equalization
3 112 Gb/s 16 nm Silicon Implementation
3.1 Receiver
3.2 Clocking
3.3 Measurement Results
4 Conclusions
References
16 BiCMOS-Integrated Circuits for Millimeter-Wave Wireless Backhaul Transmitters
1 Introduction
2 Reconfigurable Multi-core Voltage Controlled Oscillator
2.1 Multi-Core VCO Overview
2.2 Effect of Components Mismatch
2.3 VCO Measurement Results
3 Frequency Tripler with High Harmonics Suppression
3.1 Tripler Operating Principle
3.2 Tripler Design and Measurements
4 Wideband I/Q LO Generation with Self-tuned Polyphase Filter
4.1 I/Q LO Generation Architecture and Circuits Design
4.2 I/Q LO Measurement Results
5 E-Band Common-Base PAs Leveraging Current-Clamping
5.1 Principle of Current-Clamping
5.2 PAs Design and Measurements
6 Conclusions
References
17 Optical Communication in CMOS—Bringing New Opportunities to an Established Platform
1 Introduction
2 Schottky Photodiodes in Bulk CMOS
2.1 Electrical Characterization
2.2 Optical Characterization
3 Integrated Receivers Without Equalization
4 Integrated Receivers with Equalization
5 CMOS 1310/1550nm Receiver Chip Implementations
5.1 Receivers Without Equalization
5.2 Receiver with Embedded IIR DFE
6 Conclusions
References
18 Coherent Silicon Photonic Links
1 Introduction
2 Coherent Transceiver Operation
2.1 Transmitter
2.2 Receiver
3 High-Swing Linear Driver
4 Measurement Results
5 Conclusions
References
Index